View S5L9250B01-Q0R0_625016.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
S5L9250B
INTRODUCTION
The CD-ROM 48X 1 chip receives the input signal read from the CD-DA/VIDEO-CD/CD-ROM disc after handling by the RF amplifier. The signal is input into the digital servo block which has a built-in DSP core, and goes through focus and tracking adjustments. The RF signal input into a data path goes through the data slicer, PLL, EFM demodulator, C1/C2 ECC and the audio handling block. In the case of a CD-DA, the signal is output through the 1-bit DAC. In the case of a CD-ROM, the signal is input into an external CD-ROM controller for handling, then transmitted to the host through the ATAPI I/F. Also, if you operate the CD-DA in audio buffering mode while already in CAV mode, the signal is stored in the CD-ROM controller DRAM at high speed, then output at 1x from the CD-ROM controller, after passing through the 1-bit DAC built-in to the S5L9250B.
FEATURES
* Main Features Digital servo, CD-DSP, 1-bit DAC. 33.8688MHz crystal. Supports CLV 4X and 8X. Supports CAV MAX 16X, 20X, 24X, 32X, 40X, and 48X. Interrupt (SINTB) MICOM interface Digital Servo Block Automatic adjusting feature (focus/tracking loop offset, balance, loop gain) Built-in AGC feature that adapts to work optimally with various disc types Built-in search algorithm for speed control Servo monitor signal generation (FOK, MIRROR, TZC, ANTI-SHOCK) Various loop filter coefficient selection by MICOM Built-in algorithm for handling defects/shocks Disc discriminating data out (FEpk, SBADpk) RF IC and serial interface Built-in 10-bit DAC (Focus/Tracking/SLD) OAK DSP core
*
*
CD Digital Signal Processing Block Wide capture range analog PLL Data Slicer using duty feedback method EFM demodulation Sync detection, protection, insertion CLV, CAV disc spindle motor control C1/C2 ECC Built-in 16 K SRAM for ECC Subcode P - W handling feature CD-DA Audio handling feature SUB-Q De-interleaving & CRC check High speed data transmission support by CD-ROM decoder block for audio buffering (sync mode selection between subcode sync and CD-DA data) Digital audio out block Subcode sync. Insertion, Protection
1
S5L9250B
DATA SHEET
*
1-Bit DAC 16-bit digital-to-analog converter On-chip analog postfilter Filtered line-level outputs, linear phase filtering 90dB SNR Sampling rate: 44.1kHz Input rate 1Fs or 2Fs by normal mode/ double mode selection Digital volume control by MICOM interface On-chip voltage reference Digital de-emphasis on/off, digital attenuation Low clock jitter sensitivity Technology & Gate Density 0.35um mixed mode CMOS technology 3.3V power supply (internal core & analog) 5.0V power supply (digital I/O) Current used: 300mA Package: 128QFP. Core used: OAK DSP; ADC for servo use; DAC, 1-bit DAC; 16K SRAM. Clock used: 1) 33.8688MHz & PLL clock (4.3218MHz * speed coeff.) DP part. 2) 33.8688MHz or 40MHz synthesized frequency servo part. 3) 16.9344MHz 1-bit DAC part.
*
ORDERING INFORMATION
Device S5L9250B01-Q0R0 Package 128-QFP-1420C Operating Temperature -20C - +75C
2
DATA SHEET
S5L9250B
CD-ROM 48X 1 CHIP (DSP+SERVO+1-BIT DAC) BLOCK DIAGRAM
XI
XO 33.8688MHz
RF Signal
Timing Generator Data Slicer Servo Part PLL (bit clock regenerator) EQ Control Voltage Generator EFM Demodulator Sync Detector Memory Control Subcode Processing Block EQ CTL To Servo Spindle Control FG From Servo D/Audio Out Sub-Q Handling Block Subcode I/F PSC CMD D/Filter & 1-bit DAC Analog Audio Micom I/F nX-to-1X CD-DA Signal Subcode I/F Digital Audio
To Motor
I/O Signal
Glue Logic Data RAM 512 * 16*2
ROM 8K Word
OAK Core Various Error Signals From RF 10-bit ADC
SRAM for ECC
C1/C2 ECC Analog Block PWM Block TPWM 1 FOD Sled 0 TRD Sled 1 CD-DSP Part 10-bit DAC*4
Audio Processing Block
DSP I/F
Micom I/F
3
S5L9250B
DATA SHEET
PIN CONFIGURATION
EQCTL VCCA1(VCCA) RFI LPF0 LPF1 VCCA7(VCCA) EFMCOMP VSSA7(VSSA) RISS VALGC VCCA6(VSSA) RVCO RDAC VSSA6(VSSA) VCTRL VCCA5(VCCA) VBG PWMI PWMO VSSA5(VSSA) VHALF VREF VCCA4(VCCA) AOUTR AOUTL VSSA4(VSSA) VSSA1-VSSA VREFI VSSA2-VSSA RFRP RFCT SBAD CEI TZCA TE TELPF FE FELPF VCCA2-VCCA AOUT PPUMP VSSA3-VSSA TRD FOD SLED0 SLED1 SPINDLE VREFO VCCA3-VCCA SMON DVSS1-VSSOP GPIO0 SSTOP/GPIO1 PS1/GPIO2 FG DIRROT DVDD2-VDD3I RFEN RFDATA RFCLK DVSS2-VSSI DFCTI TEST1 DVDD1-VDD5OP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
Data Slicer Part
PLL Part
i-Bit DAC Part
Motor IF
KS9250 S5L9050B EVT3 EVT3 PIN DIAGRAM PIN DIAGRAM
Monitor Part
Micom IF Micom IF X'tal
LRCKI SDATAI VDDD1-VDD3I BCKI VSSD1-VSSI SCORO DVSS12-VSSOP CK50M DVDD11-VDD3I WFCKO SBSO DBDD11-VDD5OP EXCK DAOUT DVSS11-VSSOP BCKO C2PO DVSS10-VSSI LRCKO SDATAO GFS EFML/SL DVSS9-VSSOP CLVLOCK PLCK/EMPH PLOCK DVDD8-VDD3I SCANEN DVSS8-VSSI AD0 AD1 AD2 AD3 AD4 AD5 AD6 DVDD7-VDD5OP AD7
RF Interface
From RF
4
TPWM1/GPIO3 CKO TEST2 TEST3 DVDD2A(VDD3I) TEST4 TZCO/GPIO4 MIRR/GPIO5 PHOLD/GPIO6 DVSS4(VSSI) COUT/GPIO7 FOKB/GPIO8 SENSE DVDD3(VDD5OP) XI XO DVSS5(VSSOP) SINTB ZRST WRB/RWB DVDD4(VDD3I) RDB/DSB ALE/RSB DVSS7(VSSOP) CSB DVSS6(VSSI) NOTES: 1. P1 - P23: Analog 2. P24 - P102: Digital 3. P103 - P128: Digital
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
RF IF
CD-ROM Decoder IF
DATA SHEET
S5L9250B
PIN DESCRIPTION
Table 1. Pin Description No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Name VSSA1 VREFI VSSA2 RFRP RFCT SBAD CEI TZCA TE TELPF FE FELPF VCCA2 AOUT PPUMP VSSA3 TRD FOD SLED0 SLED1 SPINDLE VREFO VCCA3 SMON DVSS1 GPIO0 STOP/GPIO PS1/GPIO FG Description Analog ground (EQ controller) VREF input Analog ground (for servo ADC use) RF envelope signal RF envelope's center detection signal Related Block SERVO SERVO SERVO I/O P I P I I I I I I I I I P O O P O O O O O O P O P B SERVO SERVO CLV B B I Pad Type VSSA PICA VSSA PICA PICA PICA PICA PICA PICA PICA PICA PICA VCCA POBA POBA VSSA POBA POBA POBA POBA POBA POBA VCCA PHOB4 VSSOP PHBCT4 PHBCT4 PHBCT4 PHIC MOTOR To/From RF RF RF RF RF RF RF RF MONI DRV DRV DRV DRV SLED MOTOR -
FOK, DFCT generating SUB-BEAM ADD SERVO signal (E+F) ERROR signal for center servo use TZC signal generating signal (=TE) Tracking error signal TE defect holding pin Focusing error signal FE defect holding pin Analog 3.3V power (for servo ADC use) Analog out Pump out for PLL use (filter) Analog ground (for servo DAC use) Tracking drive signal (10-bit DAC) Focusing drive signal (10-bit DAC) Stepping control signal 0/DC motor control signal Stepping control signal 1 Spindle controlling PWM output VREF out for driver IC Analog 3.3V power (for DAC use) Spindle motor on/off Digital GND (for output PAD + PRE driver) General purpose I/O 0 LIMIT switch/sled position sensor PS0/general purpose I/O Sled position sensor signal 1/general purpose I/O Frequency generator signal (for CAV) SERVO SERVO SERVO SERVO SERVO SERVO SERVO SERVO SERVO SERVO SERVO SERVO CLV SERVO CLV -
5
S5L9250B
DATA SHEET
Table 1. Pin Description (Continued) No 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Name DIRROT DVDD2 RFEN RFDATA RFCLK DVSS2 DFCTI TEST1 DVDD1 PWM1/ GPIO CKO TEST2 TEST3 DVDD2A TEST4 TZCO/GPIO MIRR/GPIO PHOLD/ GPIO DVSS4 COUT/GPIO Description Spindle disc rotation direction Digital 3.3 V power (for internal logic use) RF data enable RF serial data RF Interface clock Digital ground (for internal logic use) Defect detection signal Test mode select Digital 5.0V power (for output PAD + PRE driver) PWM (TPWM1) output (sled monitor)/general purpose I/O 3 33.8688MHz CK out Test mode select Test mode select Digital 3.3V power (for servo SRAM use) Test mode select Track zero cross signal/general purpose I/O MIRROR signal/general purpose I/O ATSC+DFCT+KICK signal/general purpose I/O Digital ground (for servo SRAM use) COUT signal/L_MIRR signal/general purpose I/O TEST TEST TEST SERVO SERVO SERVO SERVO SERVO SERVO CLK CLK MICOM Related Block CLV SERVO SERVO SERVO SERVO TEST SERVO I/O I P O O O P I I P B O I I P I B B B P B B O P I O P O Pad Type PHIC VDD3I PHOB4 PHOB4 PHOB4 VSSI PHIS PHICD50 VDD5OP PHBCT4 PHOB8SM PHICD50 PHICD50 VDD3I PHICD50 PHBCT4 PHBCT4 PHBCT4 VSSI PHBCT4 PHBCT4 PHOD4U VDD5OP PHSOSCHF PHSOSCHF VSSOP PHOB4 MONI MONI MONI MONI MICOM MICOM OSC OSC MICOM To/From MOTOR RF RF RF RF -
FOKB/ GPIO FOCUSING ok signal/general purpose I/O SENSE DVDD3 XI XO DVSS5 SINTB Servo processor's status monitor signal Digital 5.0V power (for output PAD + PRE driver) System clock signal input pin System clock signal output pin Digital ground (for output PAD + PRE driver) Microprocessor disc interrupt (data processor)
6
DATA SHEET
S5L9250B
Table 1. Pin Description (Continued) No 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Name ZRST WRB/RWB DVDD4 RDB/DSB ALE/RSB DVSS7 CSB DVSS6 AD7 DVDD5 AD6 AD5 AD4 AD3 AD2 AD1 AD0 DVSS8 SCANEN DVDD8 PLOCK PLCK CLVLOCK DVSS9 EFML/SL GFS SDATAO LRCKO DVSS10 System reset Microprocessor write strobe (INTEL)/ read-write strobe (MOTOROLA) Digital 3.3V power (for internal logic use) Microprocessor read strobe (INTEL)/ data strobe signal (MOTOROLA) Microprocessor address latch enable/ address register select in indirect mod Digital ground (for output PAD + PRE driver) Chip select Digital ground (for internal logic use) Microprocessor address[7]/DATA BUS[7] Digital 5.0V power (for output PAD + PRE drive) Microprocessor address[6]/DATA BUS[6] Microprocessor address[5]/DATA BUS[5] Microprocessor address[4]/DATA BUS[4] Microprocessor address[3]/DATA BUS[3] Description Related Block MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM I/O I I P I I P I P B P B B B B B B B P I P O B O P O O O O P Pad Type PHIS PHISU50 VDD3I PHISU50 PHISU50 VSSOP PHISU50 VSSI PHBCT4 VDD5OP PHBCT4 PHBCT4 PHBCT4 PHBCT4 PHBCT4 PHBCT4 PHBCT4 VSSI PHICD50 VDD3I PHBCT4 PHBCT12SM PHOB4 VSSOP PHOB8SM PHOB4 PHOB12SM PHOB4 VSSI To/From MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MICOM MONI MONI MONI MONI MONI ATAPI ATAPI -
Microprocessor Address[2]/DATA BUS[2] MICOM Microprocessor Address[1]/DATA BUS[1] MICOM Microprocessor Address[0]/DATA BUS[0] MICOM Digital ground (for internal SRAM: SRAM for DP ECC use) Enable pin during scan mode test Digital 3.3V power (for internal SRAM use: SRAM for DP ECC) PLL lock indicator with HYSTERISIS Channel bit clock(O)/EMPH(I) CLV lock output Digital ground (for output PAD + PRE drive) Latched EFM signal(O) Good frame sync detection flag Serial data output Sample rate clock Digital ground (for internal logic use) TEST PLL PLL CLV PLL EFM AUDIO AUDIO -
7
S5L9250B
DATA SHEET
Table 1. Pin Description (Continued) No 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Name C2PO BCKO DVSS11 DAOUT EXCK DVDD11 SBSO WFCKO DVDD11 CK50M DVSS12 SCORO VSSD1 BCKI VDDD1 SDATAI LRCKI VSSA4 AOUTL AOUTR VCCA4 VREF VHALF VSSA5 PWMO PWMI VBG VCCA5 VCTRL VSSA6 Description C2 error pointer Bit clock Digital ground (for output PAD + PRE drive) Digital audio out Subcode data readout clock Digital 5.0V power (for output PAD + PRE drive) Subcode P TO W serial output Delayed WFCK (write frame clock) Digital 3.3V power (for internal logic use) 1-BIT DAC system clock from KS9246 Digital ground (for output PAD + PRE drive) When either S0 or S1 is detected, SCORO is high (subcode block sync) Digital ground (1-bit DAC) Bit clock input Digital 3.3V power (1-bit DAC) Serial digital Input data Sample rate clock input Analog ground (1-bit DAC) Analog output for L-CH Analog output for R-CH Analog 3.3V power (1-bit DAC) Reference voltage output for bypass Reference voltage output for bypass Analog ground (PLL_L) ALGC carrier frequency controlling output ALGC carrier frequency controlling input PLL band gap reference monitoring output Analog 3.3V power (PLL_L) VCO control voltage Analog ground (PLL_S) Related Block AUDIO AUDIO D/AUDIO SUB SUB SUB DAC SUB DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC PLL PLL PLL PLL PLL PLL PLL I/O O O P O I P O O P I P O P I P I I P O O P O O P O I O P I P Pad Type PHOB4 PHOB12SM VSSOP PHOT8 PHIC VDD5OP PHOB4 PHOB4 VDD3I PHIC VSSOP PHOB4 VSSI PHIC VDD3I PHIC PHIC VSSA POBA POBA VCCA POBA POBA VSSA POBA PICA POBA VCCA PICA VSSA To/From ATAPI ATAPI ATAPI ATAPI ATAPI ATAPI ATAPI ATAPI ATAPI SPEAKER SPEAKER -
8
DATA SHEET
S5L9250B
Table 1. Pin Description (Continued) No 116 117 118 119 120 121 122 123 124 125 126 127 128 Name RDAC RVCO VCCA6 VALGC RISS VSSA7 EFMCOMP VCCA7 LPF1 LFP0 RFI VCCA1 EQCTL Description Biasing resistor for IDAC at charge pump VCO V/I converting resistor Analog 3.3V power (PLL_S) ALGC PWM LPF output (external, DC voltage, analog level) VCO bias resistance Analog ground (data slicer) Duty feedback slicer output Analog 3.3V power (data slicer) LPF input (CD X20, X40) LPF input (CD X1, X2, X4, X8) Eye pattern from RF Analog 3.3V power (EQ controller + motor I/F (P1-5)) EQ output voltage Related Block PLL PLL PLL PLL PLL SLICER SLICER SLICER SLICER SLICER SLICER EQCTL I/O I I P I O P O P I I I P O Pad Type PICA PICA VCCA PICA POBA VSSA POBA VCCA PICA PICA PICA_25_ S5L9250B VCCA POBA To/From MONI RF RF
9
S5L9250B
DATA SHEET
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS Item DC supply voltage DC input voltage: 3.3V (internal) : 5.0V I/O DC input current Storage Temperature Symbol VDDmax Vin3 Vin5 Iin Tstg Spec. -0.3 to +7.0 -0.3 to 3.6 -0.3 to 5.5 10 -40 to 125 mA C Unit V V
ELECTROSTATIC CHARACTERISTICS Human Body Mode Item VDD positive/negative VSS positive/negative Spec. 2000V 2000V Note
MM (Machine Model) Mode Item VDD positive/negative VSS positive/negative Spec. 300V 300V Note
CDM Method Item VDD positive/negative VSS positive/negative Spec. 800V 800V Note
10
DATA SHEET
S5L9250B
RECOMMENDED OPERATING CONDITIONS No 1 2 DC supply voltage Item Operating temperature 3.3V 5.0V Symbol Topr VDD3 VDD5 Spec. 0 - 70 3.0 - 3.6 4.75 5.25 Unit C V V
DC CHARACTERISTICS: (VDD = 5V, VSS= 0V, Ta = 25C) ITEM 'H' input voltage1 'L' input voltage1 'H' input voltage2 'L' input voltage2 'H' input current1 'L' input current1 'H' input current2 'L' input current2 'H' output voltage1 'L' output voltage1 Tri-state output leakage current Quiescent supply current Symbol VIH(1) VIL(1) VIH(2) VIL(2) IIH(1) IIL(1) IIH(2) IIL(2) VOH(1) VOL(1) IOZ IDS Vin = VDD Vin = VSS Vin = VDD Vin = VSS IOH = -2/-4/-8mA IOL = 2/4/8mA Vout = VSS or VDD Vin = VSS -10 -10 10 -200 2.4 -10 100 -100 Test Condition MIN 3.5 2.0 TYP 0.810 10 200 -10 0.4 10 100 MAX 1.5 Unit V V V V uA uA uA uA V V uA uA Note
(1) (1) (2) (2) (3) (3) (4) (5) (6) (6) (7)
NOTES: 1. Related pins: All CMOS interface input terminals (PHIC) All tri-state bi-directional pad's input terminals (PHBCT4) 2. Related pins: All CMOS schmitt trigger input terminals (PHIS, PHISU) 3. Related pins: All input terminals, bi-directional pad's input mode terminals. 4. Related pins: All input buffers with pull-down. 5. Related pins: All input buffers with pull-up. 6. Related pins: All output terminals. 7. Related pins: Tri-state output buffer (PHBCT4)
11
S5L9250B
DATA SHEET
AC CHARACTERISTICS
DATA SLICER Item RF input size Input resistance Symbol Min Vrf Rin0 Rin1 Rin2 Rin3 Rin4 Rin5 Rin6 Rin7 Gain input resistance AMP offset Comparator open Loop duty error COMP output resistance Switch on resistance Slice level fix Output rang AMP gain Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 4 8 32 72 150 232 392 1.24V - 2.04V 0 5 10 40 90 190 290 490 6 12 48 108 228 348 588 Kohm Kohm Kohm Kohm Kohm Kohm Kohm Kohm Vref 15 Ls INLG[2:0] = 0H INLG[2:0] = 1H INLG[2:0] = 2H INLG[2:0] = 3H INLG[2:0] = 4H INLG[2:0] = 5H INLG[2:0] = 6H INLG[2:0] = 7H DTe Roc Ron -2 0 0 0 2 100 100 % ohm ohm Output current = 1m Output current = 1m Ra1 Vosa 0.5 1.05 1.4 1.75 2.1 3.5 4.55 7 28 8 -10 Typ 1.0 1.5 2 2.5 3 5 6.5 10 40 10 0 Spec. Max 1.5 1.95 2.6 3.25 3.9 6.5 8.45 13 52 12 10 Unit V Kohm Kohm Kohm Kohm Kohm Kohm Kohm Kohm Kohm mV RES[2:0] = 0H RES[2:0] = 1H RES[2:0] = 2H RES[2:0] = 3H RES[2:0] = 4H RES[2:0] = 5H RES[2:0] = 6H RES[2:0] = 7H Conditions
12
DATA SHEET
S5L9250B
EQUALIZER CONTROL Item F/V gain F/V linearity DAC resolution DAC linearity DAC velocity Manual control voltage Symbol MIN Kfv FVlin VLS Li Ts -2 2.17 15.35 -7 TYP 16.5 26 2 14.76 Spec. MAX 17.66 7 Unit mV/% % mV LSB uS DAC output range: 0.25 x VDD - 0.75 x VDD Conditions
Output range: 0V - 3.3V
PLL Item Pump UP current absolute value Pump DN current absolute value Pump UP/DN current matching 1 Pump UP/DN current matching 2 VCO oscillating frequency high VCO oscillating frequency low Frequency division ratio 1 Frequency division ratio 2 Frequency division ratio 3 Frequency division ratio 4 Frequency division ratio 5 Frequency division ratio 6 Frequency division ratio 7 Frequency division ratio 8 Frequency division ratio 9 CD lock check Symbol Min IPU IPD IP1 IP2 OSCH OSCL f40 f32 f28 f24 f20 f16 f8 f4 f1 CDOK 2.1 -2.5 200 20 2.8 Typ 2.3 -2.3 5 5 45 45 30 30 22.5 22.5 15 7.5 1.875 3.8 Spec Max 2.5 -2.1 10 10 250 50 Unit mA mA % % MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz V Conditions
13
S5L9250B
DATA SHEET
ARCHITECTURE DESCRIPTION
DIGITAL SERVO Characteristics * CD-ROM MAX 48X: CLV: 4X, 8X CAV: MAX 12X, 16X, 20X, 24X, 32X, 40X, 48X. Servo automatic adjustment: F/T/SBAD offset, tracking balance, focus bias, F/T loop gain F/T input AGC feature that adapts to work with various disc types at an optimum level Track search algorithm using speed control method Algorithm for handling defects and shocks Generates various servo monitor signals: FOK, MIRR, TZC, and ATSC. Built-in 10-bit ADC (8ch division): Samples FE/TE/various channels (1/16int.handling) three times at each fs. Built-in 4ch 10-bit DAC (for fod/trd/sled0, sled1 use) Disc discriminating data out (FEpk, SBADpk) Built-in 16-bit H/W track counter MICOM I/F feature: 8-bit parallel interface Serial interface with serial interface Various automatic adjusting control signals, LD on/off, etc. Each loop filter's coefficient selection possible through MICOM: focus normal/down, tracking normal/up, sled filter, various average value filter, BPF for ATSC use, BPF for loop gain automatic adjustment, etc. Sampling frequency: 176.4kHz System clock: 33.8688MHz 3.3V & 5.0V dual power
* * * * * * * * * * * *
* * *
14
DATA SHEET
S5L9250B
Block Diagram
FELPF TELPF TZCA GPIO4/TZCO VREFO TE FE AOUT GPIO7/COUT
Analog & 10-bit ADC (bw1217l_cd) Interface Block
PLL (al2002la) Timing Generator
GPIO6/PHOLD GPIO8/FOKB DFCTI ZRSTB LOCK SMON FG DIRROT GPIO2/PS1 GPIO1/SSTOP I/O Interface BLock RF Interface Block RFDATA RFCLK RFEN
RFRP RFCT GPIO5/MIRR SBAD VREFI CEI
PPUMP
XI
Track Counter
Micom Interface Block (Intel/Motorola) DSP Core SSP 1820 (OAKCORE)
FOD TRD SLED0 SLED1
SENSE WRB/RWB RDB/DSB ALE/RSB CSB AD[7:0]
10-bit DAC (bw1244d) Converter Block
GPIO3/TPWM1
PWM Generator
ROM 8K VROM_8192X16m32b2
15
S5L9250B
DATA SHEET
Block Description * Analog (A/D) interface block: This block receives servo errors such as focus and tracking errors, and carries out input gain control functions such as A/D conversion in order to heighten the rate of ADC deconstruction. It also has a TZC, a MIRR comparator feature, a VREF generating feature, and a built-in 8ch dividing MUX. Timing generator: The timing generator generates various timings used within the servo utilizing the external crystal 33.8688MHz. It also uses the built-in PLL's 40MHz as the basic signal for timing generation. I/O interface block: This block accepts externally generated signals such as lock and SSTOP, and outputs internally generated signals. It outputs various monitor signals such as ATSC and FOKB. RF interface block: This block transmits various automatic adjustment outputs and data needed by the RF, such as focus/tracking offset, TBAL output, AGC output, LD on/off, MICOM data, etc. MICOM interface block: This block relays data between MICOM and 8-bit parallel. Track counter: The track counter has a built-in 16-bit up/down counter to act as an accurate counter during jump. It is 16-bit, allowing for full stroke counting. DA converter block: This block uses a 10-bit DAC (R-string) to control the focus/tracking/sled0/sled1 at high resolution. Spindle PWM output: This output is a 1-channel PWM output for spindle control (possible with sled) ROM: This ROM is a servo program ROM with a built-in servo control program. DSP core for digital servo: This block is central to the servo. It digitally handles various emergencies such as focus/tracking loop filter handling, tracking jump, and sled move.
*
*
*
* *
* * * *
16
DATA SHEET
S5L9250B
Register MAP and Bit Description 40x Servo Command Set for CD-ROM Table 2. Register MAP and Bit Description Name STPcmd DDTcmd FONcmd TONcmd SLDcmd TRJcmd SMVcmd RPTcmd CJNCcmd FGAcmd TGAcmd OFAcmd TBAcmd HWofst FBAcmd ADScmd ADS1cmd DScmd DS1cmd DS2cmd JMDcmd JMD1cmd JMD2cmd JMD3cmd JMD4cmd EMEcmd SenLcmd Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E Description Stop command: Stops jump or other auto adjustment-related actions. Disc detect command: Detects disc presence and carries out focus search. Focus on command: Turns focus on through focus pull-in motion. Track on command: Turns tracking on or off. Sled command: Controls the sled motor. Track jump command: Carries out track jump using the track counter. Sled move command: Carries out sled move using the track counter. Repeat jump command: Carries out interval jump using the track counter. (Reserved). (Reserved). (Reserved). CD jump number common command: Designates track number. Focus gain adjustment command: Automatically adjusts focus gain. Tracking gain adjustment command: Automatically adjusts tracking gain. Offset adjustment command: Automatically adjusts offset of TE/FE/SBAD. Tracking balance adjustment command: Automatically adjusts tracking balance. HWOFST (for center point control) adjustment command. Focus balance (= bias) adjustment command: Automatically adjusts focus balance. Address setting command: Carries out upper address setting of RAM inside D-servo. Address setting1 command: Sets and prepares to read lower address of RAM inside D-servo. Data setting command: Decides address status after RAM write within D-servo. Data setting1 command: Upper data write in RAM within D-servo. Data setting2 command: Lower data write in RAM within D-servo. Jump mode select command: Designate jump-related initial value. Jump mode1 select command: Designate jump-related initial value. Jump mode2 select command: Designate jump-related initial value. Jump mode3 select command: Designate jump-related initial value. Jump mode4 select command: Designate jump-related initial value. (Reserved). Emergency command: Various emergency-related setting command. If servo is active, sense is forcibly set to "L".
17
S5L9250B
DATA SHEET
Table 2. Register MAP and Bit Description (Continued) Name CEoncmd RFcmd RF1cmd HWCcmd HWC1cmd ECOcmd ECScmd ECCcmd FTSTcmd DPRWcmd DPWcmd DPW1cmd Code 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Center point servo controlling command RF command set: Transmits RF address to send serial data to the RF IC. RF1 command set: Transmits RF data to send serial data to the RF IC. Hardware control command: Controls D-servo's H/W. Hardware control1 command: Controls D-servo's H/W. (Reserved). (Reserved). (Reserved). (Reserved). (Reserved). Eccentricity counter command: Counters eccentricity when off track. Eccentricity compensation select command: Selects eccentricity compensation method when off track. Eccentricity compensation control command: Controls eccentricity compensation on/off. Focus/tracking servo filter test command: Used for measuring the digital servo's filter characteristics. Direct port read/write command: Controls input/output of H/W inside D-servo. Direct port write command: Writes upper 8-bit data on the H/W inside D-servo. Direct port write1 command: Writes lower 8-bit data on the H/W inside D-servo. Description
18
DATA SHEET
S5L9250B
DETAILED BLOCK CHARACTERISTICS Stop Command (STPcmd) This command stops jump or auto adjustment-related servo activities, or enters into stop mode. The check priority is RST>STOP>ABRT. LDON and IDLE have the same priority. Code 00 D7 RST D6 STOP D5 ABRT D4 LDON 1'st byte D3 0 D2 0 D1 0 D0 0
RST 0: Maintain current status. 1: Reset S/W (usually used during tray off). STOP 0: Maintain current status. 1: Stop (automatically adjusted value does not change). ABRT 0: Maintain current status. 1: Stop jump or adjustment-related servo activities. LDON: Laser diode on/off bit (works only in stop mode). 0: Laser diode off. 1: Laser diode on. D3-0: (Reserved). Must be set to "L".
19
S5L9250B
DATA SHEET
Disc Detect Command (DDTcmd) Laser diode is automatically turned on. To detect if a disc is present, the focus actuator searches at the designated speed using the data RAM's FSSPD(0x20) and FSDELTA(0x21). After this command, the Fepk (S-curve/2) data and SBpk (SBAD/2)'s information are stored in the buffer so that SYSCON can read it. Code 01 D7 RPT D6 DTM1, 0 D5 D4 0 1'st byte D3 FPKU D2 0 D1 0 D0 0
RPT: Repeat focus search motion (only possible when DTM1, 0 = 0, 0). 0: Carry out focus search motion only once. 1: Continue focus search motion until RPT = 0, or when STOPcmd's abort bit = 1 is accepted (maintain sense = "L"). DTM1 -DTM0: 0: Carry out focus search once (auto). 01: Move the focus actuator to Vref position. 10: Raise focus actuator. 11: Lower focus actuator. FPKU: S-curve detect location (set to 0 in manual mode). 0: Detect when down. 1: Detect when up. * Search speed can be adjusted using the RAM's FSSPD(0x20), FSDELTA(0x21), FCNTmax(0x28), and FCNTmin(0x29). Search speed (1 period) = (FCNTmax-FCNTmin)*2*FSSPD/FSDELTA/Fs * FE peak can be read through the MICOM interface after one search. * The following are the data that MICOM can refer to after DDTcmd: - FEpk: FE peak data (S-curve/2). - SBpk: SBAD peak data (SBAD/2).
D15 Fepk
D8 D7 SBpk
D0
20
DATA SHEET
S5L9250B
Focus On Command (FONcmd) This command carries out focus pull-in. The laser diode is turned on automatically. If focus is already on when this command is received, no further actions are taken. Code 02 D7 0 D6 FONU D5 0 D4 0 1'st byte D3 PIM D2 0 D1 0 D0 0
FONU: Focus pull-in location. 0: After actuator up, pull-in when down. 1: After actuator down, pull-in when up. PIM: Pull-in method. 0: Recognize FE. Use pull-in level's absolute value. 1: Recognize FE. Use pull-in level's FEPK percentage (can be set freely using kFEok(0xfe3e) and kFEpi(0xfe3f)). * Adjust search speed using the RAM's FSSPD(0x20), FSDELTA(0x21), FCNTmax(0x28), and FCNTmin (0x29). Search speed (1 period) = (FCNTmax-FCNTmin) * 2 * FSSPD/FSDELTA/Fs * If FONcmd is accepted again during play (TRon), the tracking/sled is turned off.
21
S5L9250B
DATA SHEET
Tracking On Command (TONcmd) TONcmd is a tracking pull-in command. If tracking is already on when this command is accepted, no further actions are taken. Code 03 D7 0 D6 TON D5 SLDX D4 TFSB 1'st byte D3 TOLB1-0 D2 D1 0 D0 KICK
TON: Track on/off. 0: Off. 1: On. SLDX : Sled servo on/off. 0: Sled off. 1: Turn sled servo on after a certain time interval from tracking on. TFSB: Eccentricity compensation pull-in control bit during track pull-in. 0: Normal pull-in. 1: Eccentricity compensation pull-in (count between the edges of TZC and pull-in where the frequency is low). TOLB1-0: Lens brake during track pull-in and T/F gain control enable/disable. Used for pull-in after jump using stepping motor. 0X: Off. 10: On (during normal pull-in, use the lens kick value for the lens brake time). 11: On (pull-in after the stepping motor feed kick). KICK: KICK signal control (for stepping motor sled movement). 0: Set KICK signal to "L". 1: Set KICK signal to "H".
22
DATA SHEET
S5L9250B
Sled On Command (SLDcmd) SLDcmd is a sled motor control command. Bit check starts from the home bit. Code 04 D7 HOME D6 SMOV D5 SPLY D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
HOME: SLED HOME_IN mode select 0: Normal sled control mode. 1: Auto sled HOME_IN control mode. When this bit is set, the sled motor moves backwards until it detects the LIMIT S/W. From then on, it moves forward for the time designated by tSLDhomein. SMOV, SPLY: Sled on/off and sled move control bit. 00: Sled off 01: Sled on 10: Sled forward move 11: Sled backward move D4 to 0: Reserved. Must be set to "L". When HOME = 1 (auto sled control mode), the SENSE is as shown below.
RVS SENSE LIMIT S/W ON innermost OFF
FWD
All limit sensor data when not in auto mode are output when focus is off while the sled is moving in either direction. The limit sensor choice is made at JMD1cmd's JLIM1-0. It is "L" early in the command, but becomes "H" when it reaches either the innermost or outermost circumference.
23
S5L9250B
DATA SHEET
Track Jump Command (TRJcmd) TRJcmd is a track jump command used for track kick/brake jump and track speed control jump. Code 05 D7 DIR D6 D5 D4 1'st byte D3 NUMS D2 D1 D0
DIR: Direction you want to move in using the track counter (TC). 0: Outward movement. 1: Inward movement. NUMS: Number of upper tracks you want to move (0x00 - 0x7F). * The lower jump track number is designated by CJNCcmd (0B).
24
DATA SHEET
S5L9250B
Sled Move Command (SMVcmd) SMVcmd is a sled move command that is used for sled kick/brake movement and sled speed control movement. Code 06 D7 DIR D6 D5 D4 1'st byte D3 NUMS D2 D1 D0
DIR: The direction you want to move in using the track counter (TC). 0: Outward movement. 1: Inward movement. NUMS: Number of upper tracks you want to move (0x00 - 0x7F). * The lower Jump track number is designated by CJNCcmd (0B).
1. Repeat Jump Command (RPTcmd): (Reserved). RPTcmd is an Interval track jump command that is used during a repeating jump. Code 07 D7 DIR DIR: Direction you want to move in using the track counter (TC). 0: Outward movement. 1: Inward movement. DIR: Direction you want to move in using the track counter (TC). 0: Outward movement. 1: Inward movement. NUMS: Number of upper tracks you want to move (0x00 - 0x7F). * * The lower Jump track number is designated by CJNCcmd (0B). The interval frequency is designated by MICOM as 16 bit (0xfeef). interval freq.= sampling freq (fs)/MICOM data Example) If MICOM data is h'4000, 176 kHz (fs)/h'4000 (d'16384) = 9.2 Hz D6 D5 D4 1'st byte D3 NUMS D2 D1 D0
25
S5L9250B
DATA SHEET
CD Jump Number Common Command (CJNCcmd) CJNCcmd is a command that designates the track number of TRJcmd, RPTcmd (reserved), and the lower track number of SMVcmd. Code 08 D7 D6 D5 D4 NUMS 1'st byte D3 D2 D1 D0
NUMS: The number of lower tracks you want to move (0x01 - 0xFF). Command input method for CD when executing sled move using SMVcmd. : Input in the order, 06xx 0Bxx.
Focusing Gain Adjustment Command (FGAcmd) FGAcmd is a command that adjusts the auto focus gain. Use when focus servo is on, and tracking servo on or off. Code 0C D7 FGud D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 TFGA
FGud: Auto focus gain update 0: No update 1: When changing Kfo, Kfuo after automatic adjustment, update according to the rate of change during the automatic adjustment. TFGA: Test mode for FGA 0: Normal FGA 1: Change focus gain once without regard to focus gain ok, then change back to the previous mode.
26
DATA SHEET
S5L9250B
Tracking Gain Adjustment Command (TGAcmd) TGAcmd is an auto tracking gain adjustment command. Use while both focus servo and tracking servo are on. Code 0D D7 TGud D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 TFGA
TGud: Auto tracking gain update 0: No update 1: When changing Kto, Ktuo after automatic adjustment, update according to the rate of change during the automatic adjustment. TTGA : Test mode for TGA 0: Normal TGA 1: Change tracking gain once without regard to tracking gain ok, then change back to the previous mode.
27
S5L9250B
DATA SHEET
Offset Adjustment Command (OFAcmd) OFAcmd is an auto focus/tracking/SBAD offset Adjust command that measures and adjusts focus error, tracking error, and SBAD signal. Lens location is selected by DDTcmd's DTM1-0. Code 0E D7 VREN D6 RFRP D5 SBEN D4 TRD0 1'st byte D3 FOD0 D2 CEIEN D1 TEN D0 FEN
VREN: VREF offset measurement enable bit. 0: Do not measure VREF offset. 1: Measure VREF offset. RFRP: RFRP offset measurement enable bit. 0: Do not measure RFRP offset. 1: Measure RFRP offset. SBEN: SBAD offset measurement enable bit. 0: Do not measure SBAD offset. 1: Measure SBAD offset. TRDO: Tracking DAC offset adjustment. 0: Do not adjust. 1: Adjust. FODO: Focus DAC offset adjustment. 0: Do not adjust. 1: Adjust. CEIEN: Center error offset adjustment enable bit for center point servo. 0: Do not adjust offset. 1: Adjust offset. TEN: Tracking offset adjustment enable bit. 0: Do not adjust tracking offset. 1: Adjust tracking offset. FEN: Focus offset adjustment enable bit. 0: Do not adjust focus offset. 1: Adjust focus offset. * After offset measurement, subtract the Vref offset from TRD and FOD.
28
DATA SHEET
S5L9250B
Tracking Balance Adjustment Command (TBAcmd) TBAcmd averages the MAX and MIN values of TE using eccentricity while the focus is on and tracking is off. Always use before going into play (tracking on). Code 0F D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 TTBA
TTBA: Test mode for TBA 0: Normal TBA 1: Change tracking balance once without regard to tracking balance ok, then change back to previous mode.
Hardware Offset Adjust Command (HWOFSTcmd) HWOFSTcmd is the offset adjustment command for CEI, an input signal for center point control. Code 10 D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 THW0
Adjust the offset of RF's CEI output when HWOFSTcmd is accepted. THWO: Test mode for HW offset. 0 : Normal HW offset 1: Carry out HW offset adjustment once without regard to HW offset OK, then change back to the previous mode.
29
S5L9250B
DATA SHEET
Focus Balance Adjustment Command (FBAcmd) FBAcmd uses the RF envelop signal to end focus balance adjust when the RF signal is at its maximum. Always use after focus pull-in. Code 11 D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 TFBA
TFBA: Test mode for FBA. 0 : Normal FBA. 1: Carry out focus balance once without regard to focus balance ok, then change back to the previous mode.
Address Setting Command (ADScmd) ADScmd directly accesses SRAM within the digital servo and sets the upper address during read/write. The lower address is designated by ADS1cmd. Code 12 D15 D14 D13 1'st byte D12 D11 D10 D9 D8 ADDRESS
ADDRESS: Designates upper address of X,Y data memory. * This command is used together with ADS1cmd that designates the lower address, and is thus always used as 2 bytes (ADScmd,ADS1cmd).
Address Setting1 Command (ADS1cmd) ADS1cmd directly accesses SRAM within the digital servo and sets the lower address during read/write. It is always used after ADScmd. Code 13 D7 D6 D5 D4 1'st byte D3 D2 D1 D0 ADDRESS
ADDRESS: Designates the lower address of X,Y data memory.
30
DATA SHEET
S5L9250B
Data Setting Command (DScmd) DScmd decides whether to maintain the current address or increase it by one (+1) after write, when writing data by directly accessing SRAM inside the digital servo. At this time, the SRAM address must be designated first using the ADScmd (12H). Code 14 D7 NEXT D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
NEXT: Determines X,Y data memory address status after data write. 0: X,Y data memory address becomes ADS1cmd and ADS2cmd's D15-0. 1: X,Y data memory address becomes ADS1cmd and ADS2cmd's D15-0 +1.
Data Setting1 Command (DS1cmd) DS1cmd is a command that writes upper data by directly accessing SRAM, the digital servo's internal data. Code 15 D15 D14 D13 1'st byte D12 DATA D11 D10 D9 D8
DATA: Upper DATA selection (used together with DScmd and DS2cmd).
Data Setting2 Command (DS2cmd) DS2cmd is a command that writes upper data by directly accessing SRAM, the Digital servo's internal data. Code 16 D15 D14 D13 1'st byte D12 D11 D10 D9 D8 ADDRESS
DATA: Lower DATA selection (used together with DScmd and DS1cmd).
31
S5L9250B
DATA SHEET
Jump Mode Select Command (JMDcmd) JMDcmd is a jump-related initial value selection command. Code 17 D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
Jump Mode1 Select Command (JMD1cmd) JMD1cmd is a jump-related initial value selection command. Code 18 D7 TCKS1-0 D6 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
TCKS1-0: Clock selection bit for measuring the pull-in frequency during track pull-in. 00: TZC 01: MIRR 10: L_TZC 11: L_MIRR
32
DATA SHEET
S5L9250B
Jump Mode2 Select Command (JMD2cmd) JMD2cmd is a jump-related initial value selection command. Code 19 D7 LFKS D6 FKMOD D5 FSEQ D4 FNEQ 1'st byte D3 HYS D2 TGS D1 FDC D0 0
LFKS: Lens kick / Feed move select bit. 0: Lens kick. 1: Feed move. FKMOD: When LFKS is "H", feed move type select. 0: Speed feedback type feed move. 1: Open control type feed move. FSEQ: Usage feed search EQ in feed move. 0: Do not use 1: Use feed search EQ FNEQ: Usage feed normal EQ in feed move. 0: Do not use 1: Use feed normal EQ HYS: Usage hysterisis in the end of search. 0: Do not use 1: Use hysterisis TGS: Usage tracking gain up in the end of search . 0: Do not use 1: Use tracking gain up FDC: Add initial kick value(offset) to feed output in feed move . 0: Do not add 1: Add
33
S5L9250B
DATA SHEET
Jump Mode3 Select Command (JMD3cmd) JMD3cmd is a jump-related initial value selection command. Code 1A D7 0 D6 0 D5 0 D4 0 1'st byte D3 HCRE D2 HCRC D1 D0 HCRS
HCRE: Hardware counter reference edge. 0: Raising 1: Falling HCRC: Hardware counter reference clock. 00: CK32(1.25MHz = 800ns) 01: CK16( 2.5MHz = 400ns) 10: CK08( 5MHz = 200ns) 11: CK04( 10MHz = 100ns) HCRS: Hardware counter reference signal. 0: TZC. 1: Mirr.
34
DATA SHEET
S5L9250B
Jump Mode4 Select Command (JMD4cmd) JMD4cmd is a jump-related initial value selection command. Code 1B D15 RVSB D14 VCMP D13 VEDG 1'st byte D12 D11 VPRDR D10 D9 VCLKS D8
RVSB: Reverse check selection during jump. 0: If there are less remaining tracks than RVSnum(0xbe) during reverse, stop the jump. 1: Do not carry out reverse check. VCMP: 1 counter compensation (when count is "H"). 0: Do not compensate. 1: Compensate. VEDG: Standard edge selection for the velocity jump period counter. 00: Falling & Rising 01: Falling 10: Rising 11: Falling & Rising VPRDR: Velocity jump period standard signal (H/W counter and kick/brake standard clock also change). 00: TZC 01: MIRR 10: L_TZC (L_MIRR selected for H/W counter and kick/brake standard clock). 11: L_MIRR VCLKS: Velocity clock select 00: CK32 (1.25MHz = 800ns) 01: CK16 (2.5MHz = 400ns) 10: CK08 (5MHz = 200ns) 11: CK04 (10MHz = 100ns)
Jump Mode5 Select Command (JMD5cmd) : Reserved JMD5cmd is a jump-related initial value selection command. Code 1C D15 0 D14 0 D13 0 0 1'st byte D12 D11 0 D10 0 D9 0 D8 0
35
S5L9250B
DATA SHEET
Emergency Command (EMEcmd) EMEcmd handles emergencies such as shock. Code 1D D7 FATS D6 TATS D5 LATS D4 SLOCK 1'st byte D3 0 D2 0 D1 0 D0 0
FATS: The bit that decides whether or not to change focus gain during a shock. 0: Maintain focus gain at normal. 1: Change focus gain. TATS: The bit that decides whether or not to change tracking gain during a shock. 0: Maintain tracking gain at normal. 1: Change tracking gain. LATS: Lens brake control bit during anti-shock. 0: Lens brake off. 1: Lens brake on. SLOCK: Sled control bit when lock signal is off. 0: Stop sled. 1: Do not stop sled.
Sense L Command (SenLcmd) Forcibly sets sense to "L" during a servo command. Code 1E D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
When a command is accepted to read internal RAM data while a servo command such as gain control is being executed, sense becomes "H" even when the servo command is not yet finished. In such a case, the SenLcmd checks the internal status and reconsiders sense status.
36
DATA SHEET
S5L9250B
Center Point Servo Control Command (CEcmd) CEcmd controls the center point servo. Code 1F D7 CEonb D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
CEonb: Center point servo control bit. 0: Center point servo filter on. 1: Generate center point brake signal (output level and time are decided by CEbrklvl(170h) and CEbrkTM(171h)).
37
S5L9250B
DATA SHEET
RF Command (RFcmd) RFcmd transmits the RF address in order to send serial data to the RF IC. Code 20 D15 D14 D13 1'st byte D12 D11 D10 D9 D8 RF ADDRESS
RF address 01H: - RFEQ_SEL - MODE_SEL (CD-ROM/CD-RW) - ABCD_ATT RF address 02H: - EQG_CEN - C48_SEL - CAV_SEL - AGC_LVL RF address 03H: - AGCON - AGCIN_Z - PUP_SEL GAIN_PLLF RF address 04H: - TE_LPF - TE_ATT RF address 05H: - FE_LPF - FE_ATT RF address 06H: - SERVO_OFST RF address 07H: - TBAL RF address 08H: - RFRP_FREQ - DFT_TH - RFRP_TH RF address 09H: - SBAD_ATT RF address 0AH: - LD_ON RF address 0BH: - RFRP_SEL RF address 0FH: - PDMODE * This command is used together with RF1cmd, and thus always used as 2 bytes (RFcmd,RF1cmd).
38
DATA SHEET
S5L9250B
RF1 Command (RF1cmd) RF1cmd transmits the RF address in order to send serial data to the RF IC. Code 21 D7 D6 D5 D4 1'st byte D3 D2 D1 D0 RF DATA
When RF address = 01H: - D7-4 (RFEQ_SEL): EQ speed selection bit. - D2-0 (ABCD_ATT): ABCD ATT gain selection bit. When RF address = 02H: - D7 (reserved). - D6-4 (EQG_CEN): Center gain detailed adjustment selection bit for EQ boost gain. - D3 (C48_SEL): 4x, 8x selection bit. 0: 4x 1: 8x - D2 (CAV_SEL): CAV, CLV selection bit. 0: CAV 1: CLV - D1-0 (AGC_LVL): RFAGC amp output level selection bit. When RF address = 03H: - D7(AGCON) : RF AGC 0N/OFF selection bit. 1: RFAGC ON 0: RFAGC OFF - D6-4(AGCIN_Z): RFAGC input impedance selection bit. - D3 (PUP_SEL) : RF_SUM or A, B, C, D selection bit. 0: RFSUM pick_up 1: A, B, C, D pick_up - D2-0 (GAIN_PLLF): Selection bit for RF EQPEAK frequency change sensitivity according to PLLF voltage. When RF address = 04H: - D7-6 (reserved). - D5-4 (TE_LPF): TE LPF frequency selection bit. - D3 (reserved). - D2-0 (TE_ATT): TE ATT gain selection bit. When RF address = 05H: - D7-6 (reserved). -D7-6 (FE_LPF): FE LPF frequency selection bit. - D3 (reserved). D2-0 (FE_ATT): FE ATT gain selection bit. When RF address = 06H: D7-0 (SERVO_OFST): Servo offset control bit. When RF address = 07H: - D7-0 (TBAL): Tracking balance control bit.
39
S5L9250B
DATA SHEET
When RF address = 08H: - D7-6 (RFRP_FREQ): RFRP peak-bottom hold frequency selection bit. - D5-3 (DFT_TH): Defect slice level selection bit. - D2-0 (RFRP_TH): RFRP slice level selection bit. When RF address = 09H: - D7-3 (reserved). - D2-0 (SBAD_ATT): SBAD's output gain selection bit. When RF address = 0AH: - D7-1 (reserved). - D5 (LD_ON) : LD's on/off selection bit. 0: LD OFF 1: LD ON When RF address = 0BH: - D7-1 (reserved). - D0 (RFRP_SEL): RFRP block output selection bit. 0: RFRP, RFCT 1: ENVELOPE When RF address = 0FH: - D7-1 (reserved). - D4 (MODE_SEL): CD-RW, CD-ROM selection bit. 0: CD-RW 1: CD-ROM - D0 (PDMODE): Power down mode selection bit. 0: Power down mode 1: Normal mode
40
DATA SHEET
S5L9250B
Hardware Control Command (HWCcmd) HWCcmd controls the H/W inside the Digital Servo. Code 22 D7 0 D6 D5 SINT2-0 D4 1'st byte D3 D2 D1 D0 HTDEN1-0 HFDEN1-0
FRSEL: (D7 reserved). Free running counter select. 0: INT1 select (4-bit counter) 1: INT2 select (3-bit or 2-bit counter according to INTSEL1) SINT2-SINT0: INT1's division rate selection. 000: INT1b = XIN / 192 - default 001: INT1b = XIN / (192+16*1) 010: INT1b = XIN / (192+16*2) -- : -111: INT1b = XIN / (192+16*7) HTDEN1-0: Tracking defect handling enable bit. 00: Do not use tracking defect handling. 01: Always use tracking defect handling when a defect is found. 10: Use tracking defect handling only when CLV lock. 11: Do not use tracking defect handling. HFDEN1-0: Focus defect handling enable bit. 00: Do not use focus defect handling. 01: Always use focus defect handling when a defect is found. 10: Use focus defect handling only when CLV lock. 11: Do not use focus defect handling. * This command is used together with HWC1cmd, and is always used as 2 bytes (HWCcmd, HWC1cmd).
41
S5L9250B
DATA SHEET
Hardware Control1 Command (HWC1cmd) HWC1cmd controls the H/W inside the digital servo. Code 23 D7 0 D6 0 D5 DACEN D4 0 1'st byte D3 1 D2 HDFMK D1 HKSMK D0 HSHMK
DACEN: DAC output enable. 0: VREF output to DAC. 1: Normal DAC. HDFMK: Chooses whether or not to output the defect signal to the PHOLD pin. 0: Do not output defect signal (default). 1: OR the shock signal, kick and defect signal, then output. HKSMK: Chooses whether or not to output the kick signal to the PHOLD pin. 0: Do not output kick signal (default). 1: OR the shock signal, defect and kick signal, then output. HSHMK: Chooses whether or not to output the shock signal to the PHOLD pin. 0: Do not output shock signal (default). 1: OR the defect signal, kick and shock signal, then output.
Eccentricity Counter Command (ECOcmd) ECOcmd counts tracking errors for one disc revolution, for the purpose of measuring the amount of eccentricity for eccentricity compensation during OFF track status. Code 29 D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
The counted value is stored in data RAM 49h.
42
DATA SHEET
S5L9250B
Eccentricity Compensation Select Command (ECScmd) ECScmd selects the eccentricity compensation method. The eccentricity compensation routine starts automatically when this command is accepted. Code 2A D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
Stores and uses the eccentricity value for one disc revolution at each fs/N.
Eccentricity Compensation Control Command (ECCcmd) ECCcmd controls the eccentricity compensation ON/OFF. Code 2B D7 ECC D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
ECC: Eccentricity compensation ON/OFF control bit. 0: OFF. 1: ON.
Focus/Tracking Servo Filter Test Command (FTSTcmd) FTSTcmd is a test command for measuring the digital servo's filter characteristics. Code 2C D15 0 D14 0 D13 0 1'st byte D12 WTF D11 0 D10 0 D9 0 D8 WFF
WTF: Tracking filter test. 0: Tracking filter normal test. 1: Tracking filter up test. WFF: Focus filter test. 0: Focus filter normal test. 1: Focus filter down test. * However, the input of the sled filter test becomes TE.
43
S5L9250B
DATA SHEET
Direct Port Read/Write Command (DPRWcmd) DPRWcmd is a command for directly reading the IN/OUT buffer within the digital servo, or writing DPWcmd and DPW1cmd's 16-bit data. Code 2D D7 WRB D6 D5 D4 1'st byte D3 DPS6-0 D2 D1 D0
WRB: IN/OUT buffer read/write selection. 0: Read the IN/OUT buffer inside the digital servo. 1: Write DPWcmd and DPW1cmd's 16-bit data on the IN/OUT buffer inside the digital servo. DPS6-0: Chooses which port to read/write, combined with WRB. * * This command inputs DPWcmd that shows the upper address and the DPW1cmd that shows the lower address, and uses them as a total of 3 bytes. Data Read
h'2D00: Read the value of the STRD1 (external status1 read) buffer. h'2D01: Read the value of the STRD (external status read) buffer. h'2D02: Read the value of the VCTRD (free running counter for 1/16 use) buffer. h'2D03: Read the value of the VCTRD1(free running counter for Dfct use) buffer. h'2D04: Read the value of the CMDRD (MICOM command read) buffer. h'2D05: Read the value of the MDRD (MICOM data read) buffer. h'2D06: Read the value of the TMCNTRD (TZC, MIRR's edge to edge counter value read for speed control) buffer. h'2D07: (Reserved). h'2D08: Read the value of the CNTRD (Hardware counter value read) buffer. h'2D09: Read the value of the ADCRD (AD conversion value read) buffer. h'2D0A: Read the value of the CLVFRD (CLV frequency data) buffer. h'2D0B: Read the value of the CLVPRD (CLV phase data) buffer. h'2D0C: Read the value of the FERD (FE AD conversion value read) buffer. h'2D0D: Read the value of the TERD (TE AD conversion value read) buffer. h'2D0E: Read the value of the CEIRD (CEI AD conversion value read) buffer. h'2D0F: Read the value of the ADI1RD (ADI1 AD conversion value read) buffer. h'2D10: Read the value of the ADI2RD (ADI2 AD conversion value read) buffer. h'2D11: Read the value of the SBADRD (SBAD AD conversion value read) buffer. h'2D12: Read the value of the RFRPRD (RFRP AD conversion value read) buffer. h'2D13: Read the value of the VREFRD (VREF AD conversion value read) buffer. h'2D14-h'2D18: (Reserved). h'2D19: Read the value of the MODATRD(GPIO 8, 7, 6, 5, 4 input data read) buffer h'2D1A-h'2D1E: (Reserved).
44
DATA SHEET
S5L9250B
*
Data Write Method
h'2D80: Write the value in the ASEL (Analog select and ADC start) buffer. h'2D81: Write the value in the TRD (DAC out for tracking drive) buffer. h'2D82: Write the value in the CTL1 (H/W control out1) buffer. h'2D83: Write the value in the CTL (H/W control out) buffer. h'2D84: Write the value in the FOD (DAC out for focus drive) buffer. h'2D86: Write the value in the SPD (9-bit PWM out for spindle drive) buffer. h'2D87: Write the value in the FIG (Focus input gain control) buffer. h'2D88: Write the value in the TIG (Tracking input gain control) buffer. h'2D89: Write the value in the SLEDO (10-bit DAC for test) buffer. h'2D8A: Write the value in the CNTRB (Tracking counter reset) buffer. h'2D8B: Write the value in the MDWR (MICOM data write) buffer. h'2D8C: Write the value in the RFCMD (RF data out) buffer. h'2D8D: Write the value in the TMCTL (TZC/MIRR divide control) buffer. h'2D8E: Write the value in the PRCNT (Reference track number setting for jump) buffer. h'2D91: Write the value in the TDFCT (Defect delay load) buffer. h'2D92: Write the value in the TLD1 (INT0b down counter1 load) buffer. h'2D93: Write the value in the TLD2 (INT0b down counter2 load) buffer. h'2D94: Write the value in the TLD3 (INT0b down counter3 load) buffer. h'2D95: Write the value in the TLD4 (INT0b down counter4 load) buffer. h'2D96: Write the value in the TLD5 (INT0b down counter5 load) buffer. h'2D97: Write the value in the TLD6 (INT0b down counter6 load) buffer. h'2D98: Write the value in the TRD_AVR (TRD average data for H/W lens brake) buffer. h'2D99: Write the value in the MODAT (GPIO 8, 7, 6, 5, 4 output write) buffer. h'2D9A: Write the value in the HWCMD (H/W command out) buffer. h'2D9B: Write the value in the SLED1 (10-bit DAC1 for test) buffer. h'2D9C: Write the value in the PLLCMD (PLL divition ratio control out) buffer. h'2D9D: Write the value in the MOCTL (GPIO 8, 7, 6, 5, 4 in/out control) buffer. h'2D9E: Write the value in the MOSEL (GPIO 8, 7, 6, 5, 4 data select) buffer. h'2D9F-2DFF: (Reserved).
45
S5L9250B
DATA SHEET
Direct Port Write Command (DPWcmd) DPWcmd is a command that shows the upper 8-bit address for writing on the IN/OUT buffer within the digital servo using DPRWcmd. Code 2E D15 D14 D13 1'st byte D12 D15-8 D11 D10 D9 D8
Direct Port Write1 Command (DPW1cmd) DPW1cmd is a command that shows the lower 8-bit address for writing on the IN/OUT buffer within the digital servo using DPRWcmd. Code 2F D7 D6 D5 D4 D7-0 1'st byte D3 D2 D1 D0
General Purpose MICOM Control Port Command (GPIOmicmd) The GPIOmicmd controls the IN/OUT of the general purpose PAD (GPIO3, GPIO2, GPIO1, GPIO0) through MICOM command. D2, D1, D0 = 1 (H/W is set as GPIO2, 1, 0 input/default), = 0 (GPIO2, 1, 0 output mode select) D3 = 1 (H/W is set as GPIO3 input/default), = 0 (GPIO3 output mode select) D4 = 0 (H/W is set as internal GPIO3 PWM output/default/ D3 = 1), = 1 (GPIO3 output mode by MICOM 3C register/ D3 = 0, mode select)
Code 3B D7 0 D6 0 D5 0 D4 gpio_pwm_en [4] 1'st byte D3 gpio3_towm1 [3] gpio_en_mi [3] D2 gpio2_PS1 [2] gpio_en_mi [2] D1 gpio1_SSTOP [1] gpio_en_mi [1] D0 gpio0-en [0] gpio_en_mi [0]
CONTROL
46
DATA SHEET
S5L9250B
General Purpose MICOM Data Read/Write Command (GPIOdatcmd: R/W) MICOM writes data on the 3-ch register and outputs DATA(md[3:0]) to the general purpose pad (GPIO3, GPIO2, GPIO1, GPIO0). (output mode is controlled by the 3Bh register.) General purpose pad (GPIO3, GPIO2, GPIO1, GPIO0)'s input status (md[3:0)) is stored in the 3-ch register so that MICOM can read it (input mode is controlled by the 3Bh register). * When reading the 3C register, GPIO3 is for PWM output and GPIO0 is for reserved Input. Code 3C D7 0 D6 0 D5 0 D4 0 1'st byte D3 md[3] D2 md[2] D1 md[1] D0 md[0]
Sled DAC Output Control Command (SLDCTLcmd) SLDCTLcmd controls the output of DAC (SLED0, SLED1). D2 = 1(SERVO DATA), = 0 (MICOM DATA)/D1, D0 = 1 (DAC VREF), = 0 (DAC DATA) output Code 3D D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 mi/servo D1 sld1 D0 sld0
SLED0 DAC MICOM Data Write Command (SLED0micmd) SLEDOmicmd writes DAC(SLED0)'s MICOM data. Code 3E D7 D6 D5 D4 1'st byte D3 D2 D1 D0 SLED0miDATA[7:0]
SLED1 DAC MICOM Data Write Command (SLED1micmd) SLED1micmd writes DAC(SLED1)'s MICOM data. code 3F D7 D6 D5 D4 1'st byte D3 D2 D1 D0 SLED1miDATA[7:0]
47
S5L9250B
DATA SHEET
DETAILED BLOCK CHARACTERISTICS General Purpose Pad < Control by MICOM Command > The control initial value is set to the default (H/W) input (address 'h3B, data 'h0F). When in input mode: Set to input mode by MICOM 'h3B0F/gpio3 PWM output, gpio2, 1, 0 input PWM output by TPWM1 or sled0 (OAK command)/PS1, SSTOP(PS0) input/reserved input When in output mode: Set to output mode by MICOM 'h3B10, then output X DATA[3:0] by MICOM 'h3CX command. PORT Control Input Output gpio3 gpio_en_mi[3] TPWM1 gpio_md[3] gpio2 gpio_en_mi[2] PS1 gpio_md[2] gpio1 gpio_en_mi[1] SSTOP(PS0) gpio_md[1] gpio0 gpio_en_mi[0] gpio_md[0]
< Control by OAK COMMAND > The control initial value is set to the default (H/W) input (MOCTL = 1). When in input mode: MOCTL = 1 (GPIO8, 7, 6, 5, 4 input). After MOSEL = 1 (input data select), set to MODAT = 1 (data latch) so that MODATRD = 1 (data read). When in input mode: MOCTL = 0 (GPIO8, 7, 6, 5, 4 output). Set to MOSEL = 0 (output data select) FOKB, COUT, PHOLD, MIRR, TZCO moniter. PORT Control Input Output gpio8 MOCTL(db[12]) Mo_data(db[4]) FOKB gpio7 MOCTL(db[11]) Mo_data(db[3]) COUT gpio6 MOCTL(db[10]) Mo_data(db[2]) PHOLD gpio5 MOCTL(db[9]) Mo_data(db[1]) MIRR gpio4 MOCTL(db[8]) Mo_data(db[0]) TZCO
48
DATA SHEET
S5L9250B
< OAK Address Decoding/Address Description > Description User IO EXT register EXT[5:0] Address 14 (ext0) 15 (ext1) 16 (ext2) 17 (ext3) 0800 0801 0802 0803 0804 0805 0806 0807 0808 0809 080A 080B Data bus address [15:0] 080C 080D 080E 080F 0810 0811 0812 0813 0814 0815 0816 0817 0818 0819 081A RF Serial Interface There are 2 methods of sending data to the RF IC: Read (IORN) STRD1 STRD VCTRD VCTRD1 CMDRD MDRD TMCNTRD CNTRD ADCRD CLVFRD CLVPRD FERD TERD CEIRD ADI1RD ADI2RD SBADRD RFRPRD VREFRD MODATRD DB_Out[15:0] dB[15:0] dB[15:0] dB[15:0] dB[15:0] dB[7:0] dB[15:8] dB[15:0] dB[15:0] dB[15:6] dB[15:0] dB[15:0] dB[15:6] dB[15:6] dB[15:6] dB[15:6] dB[15:6] dB[15:6] dB[15:6] dB[15:6] dB[4:0] Write (IOWN) ASEL TRD CTL1 CTL FOD SPD FIG TIG SLED0 CNTRB MDWR RFCMD TMCTL PRCNT TDFCT TLD1 TLD2 TLD3 TLD4 TLD5 TLD6 TRD_AVR MODAT HWCMD SLED1 PLLCMD MOCTL MOSEL DB_IN[15:0] dB[2:0] dB[15:6] dB[15:0] dB[15:0] dB[15:6] dB[15:8] dB[14:10] dB[14:10] dB[15:6] dB[15:0] dB[15:0] dB[12:0] dB[15:0] dB[15:0] dB[15:0] dB[15:0] dB[15:0] dB[15:0] dB[15:0] dB[15:0] dB[15:6] dB[12:8] dB[15:0] dB[15:6] dB[15:0] dB[12:8] dB[12:8]
49
S5L9250B
DATA SHEET
* *
MICOM: If you send 16-bit data to the XXh address of the MICOM interface within the servo, the DSP uses the RFCcmd through the RF interface to transmit data. Servo: If you write data from the servo CPU to the RFcmd, the data is transmitted through the RF interface.
However, the RF interface is a serial interface, so when you send the next RF command, you must make sure that the sense is "H" for MICOM, or that you write to RFcmd after CK6 * 20 clocks for servo. Address D15 XXh D14 D13 D12 D11 D10 D9 RF Address Data D8 D7 D6 D5 D4 D3 D2 D1 D0 RF data Notes
Serial Port Data Transfer Format
RFEN
RFDATA
Address, 8-bit
Data, 8-bit
RFCLK A7 A0 D7 D0
Serial Port Data Transfer Format
50
DATA SHEET
S5L9250B
HOME IN Summary
When using the REVERSE SLED MOVE to move the P/U from the starting point to the innermost circumference, and the PS signal does not occur after a certain amount of time, HOME IN is assumed. If so, the P/U goes into FORWARD MOVE long enough to escape the LEAD IN area and finishes the task.
Input signal : PS0, PS1 Output signal : SLD Command (0x04hh) Code 04 D7 HOME D6 SMOV D5 SPLY D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
HOME : SLED HOME_IN MODE selection 0 : Normal SLED CONTROL MODE. 1 : AUTO SLED HOME_IN CONTROL MODE. When this bit is set, the Sled Motor continues BACKWARD MOVE until it detects LIMIT S/W. From then on, it carries out FORWARD MOVE for the time designated by tSLDhomein. SMOV,SPLY : Controls Sled On/Off and Sled move. 00 : Sled Off 01 : Sled On 10 : Sled Forward move 11 : Sled Backward move D4 to 0 : Reserved. Must set to "L". For sense output excepting AUTO mode, the limit sensor data is output in focus off status during the sled's inward/outward movement. The limit sensor selection is made by JMD1cmd's JLIM1 - 0. It is "L" early in the command, but becomes "H" once it reaches the innermost/outermost circumference. Related Memory NAME SLDminus SLDplus tSLDhomein tFGchk JMD01buf ADDR. 00A0 00A1 0031 0032 001C FUNCTION Sled minus kick level Sled plus kick level Forward jump time after sled home in FG limit time Jump mode buffer (FG,L s/w select) Data 0 x F800 0 x 0800 0 x 0010 0 x 1000 Value 188mV 188mV 5.6 s*16 22.9 ms
51
S5L9250B
DATA SHEET
Operation Description The sled is moved in reverse direction. If there is no signal change in FG1 or FG0 (present) for a period of time (tFGchk), the Sled output is put into Forward Kick for the length of tSLDhomein, and reverted to Vref.
PS1 PS0 SLED0 SLED1 SLDminus SLDplus
tFGchk SENSE
tSLDhomein
HOME IN Detection by LIMIT S/W (When you have no Sled Encoder): LIM is set to "H" (sled stopped by LIMIT S/W) when there is LIMIT S/W. DSSP's PS0 pin changes its function to SSTOP, and LIMIT S/W becomes connected to this block.
Limit S/W SLDminus SLDplus
SLED0 SLED1
tSLDhomein
*
Home In Block Diagram
TE 9 fs
TEin
Tracking Loop Filter
TRDo LPF
TRD DAC 17 SLED0 DAC 19 20 Kick/brk Output Block Vref SLED1
(for anti-aliasing) fs/16
TRD_avrg TRD AVRG Filter
SLDIN Sled Loop Filter
SLDavrg
52
DATA SHEET
S5L9250B
OFFSET ADJUST * Summary
The DSSP measures and averages the FE/TE Offset between the SERVO+DSAP chip (S5L9250B) and RF chip (KS9251), stores it in the Register, then uses it in later filter operations to reduce remaining error deviations caused by offset. Output Register : Each register Command (0x0Ehh) Code 0E D7 VREV D6 RFRP D5 SBEN D4 TRDO 1'st byte D3 FODO D2 CEIEN D1 TEN D0 FEN
VREV : VREF offset measurement enable bit. 0 : Do not measure VREF offset. 1 : Measure VREF offset. RFRP : RFRP offset adjustment enable bit. 0 : Do not adjust RFRP offset. 1 : Adjust RFRP offset. SBEN : SBAD offset adjustment enable bit. 0 : Do not adjust SBAD offset. 1 : Adjust SBAD offset. TRDO : Tracking DAC offset adjustment bit. 0 : Do not adjust tracking DAC offset. 1 : Adjust tracking DAC offset. FODO : Focus DAC offset adjustment bit. 0 : Do not adjust focus DAC offset. 1 : Adjust focus DAC offset. CEIEN : Center error offset adjustment enable bit for center point servo use. 0 : Do not adjust offset. 1 : Adjust offset. TEN : Tracking offset adjustment enable bit. 0 : Do not adjust Tracking offset. 1 : Adjust Tracking offset. FEN : Focus offset adjustment enable bit. 0 : Do not adjust Focus offset. 1 : Adjust Focus offset. Subtract Vref offset from TRD and FOD after measuring the offset.
53
S5L9250B
DATA SHEET
Related Memory Name FEofst TEofst CEIofst SBADofst RFRPofst FODofst TRDofst Vref OFSTwt OFSTacc Kofstg Kofst Sofst Addr. 0090 0091 0092 0093 0094 0068 0069 0035 004E 004F FEF4 FEF5 FEF6 FE offset TE offset CEI offset SBAD offset RFRP offset FOD offset TRD offset VREF DATA offset stable time offset acculating time offset input gain K1 Shift (select) offset 0 x 0040 0 x 0100 0 x 0400 0 x 7C00 0 x 0007 Function Data Value
54
DATA SHEET
S5L9250B
DISC DETECTION Summary The Laser diode is automatically turned On. To detect disc presence, the Focus Actuator searches at a designated speed (FSSPD (0x20), FSDELTA (0x21)). The FOD outputs delta waves to move the Actuator up and down. After this command, information such as FEpk (S-curve/2)data and SBpk (SBAD/2) are stored in the buffer so that SYSCON can read it. Input signal : FE,SBAD Output signal : FOD, FOKB, MIOUT (data) Command (0x01XX) : The Laser diode is automatically turned On. To detect disc presence, the Focus Actuator searches at a designated speed (FSSPD(0x20), FSDELTA (0x21)). After this command, information such as Fepk (Scurve/2)data and SBpk (SBAD/2) are stored in the buffer so that SYSCON can read it. Code 01 D7 RPT D6 DTM1,0 D5 D4 0 1'st byte D3 FPKU D2 0 D1 0 D0 0
RPT : Repeat of Focus Search movement. 0 : Execute only once. 1 : Continue (maintain sense = "L") until receiving DDTcmd (RPT = 0). DTM1 DTM0 : 00 : Execute Focus Search once (AUTO). 01 : Move Focus Actuator to Vref location. 10 : Raise Focus Actuator. 11 : Lower Focus Actuator. FPKU : S-curve detect location (use during AUTO search). 0 : Detect when Down. 1 : Detect when Up. Search Speed is adjusted using RAM's FSSPD (0x20) FSDELTA (0x21). Search Speed = 10mv/(128fs * FSSPD/FSDELTA) After SEARCH has been executed once, FE PEAK can be read through the MICOM Interface. Data that MICOM can refer to after DDTcmd. D15 FEpk FEpk : FE peak data (S-curve/2). SBpk : SBAD peak data (SBAD/2). D8 D7 SBpk D0
55
S5L9250B
DATA SHEET
Related Memory Name DDTbuf FSSPD FSDELTA FSCNT FEMAX FEMAXp FEMIN FEMINp FEPK FSCNTmax FSCNTmin SBADMAX SBADMIN SBADPK tFSCNT FE Address 001A 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 0062 Function DDT command buffer Focus Search speed Focus Search delta Focus Search counter FE max data FECNT when FEmax FE min data FECNT when FEmin FEpp/2 Focus Search output max Focus Search output min SBAD max data SBAD min data SBADpp/2 Focus Search Wait Time Focus error 0 x 2000 0 x 1800 0 x E800 0 x 0001 0 x 0008 Data Value
56
DATA SHEET
S5L9250B
OPERATION DESCRIPTION When the Disc Detect command is input, the output signal FOD starts from the Vref voltage to output a delta waveform as shown in the figure below. At this time, Up/Down Detect is decided by Auto Search Mode. Search Speed or slope is decided by FSSPD and FSDELTA, and the upper and lower limit duration is determined by tFSCNT.
When FPKU (FEpk check on when actuator up) = 1 FSCNT [max] fod FSCNT [min]
[tFSCNT]
When FPKU (FEpk check on when actuator up) = 0 [tFSCNT] fod
SENSE
SENSE
Disc Detection Disc presence and type are detected by the Focus Search command. After command, MICOM reads FEpk and SBADpk. Disc Detection Block Diagram
Delta Wave Output Block FE 11 fs
Vref FOD
FEI
Focus Loop Filter
DAC
18
57
S5L9250B
DATA SHEET
FOCUS PULL-IN Summary Delta waves are output from FOD to move the ACTUATOR up and down. FOCUS PULL-IN is executed near the FE(S_CURVE) signal's ZERO CROSS area. Input signal : FE, SBAD Output signal : FOD, FOKB Command (0x02hhhh) : This is a Focus Pull-in enabling command. The Laser diode is automatically turned on. If focus is already on when this command is received, no further actions are taken. Code 02 D7 0 D6 FONU D5 0 D4 0 1'st byte D3 PIM D2 0 D1 0 D0 0
FONU: Focus Pull-in location. 0 : Pull-in at Down after Actuator Up. 1 : Pulll-in at Up after Actuator Down. PIM : Pull In Method. 0 : FE recognized. Absolute value of pull-in level used. 1 : FE recognized. Pull-in level's FEPK's percentage used (Can be freely set using RAM's buffer). Search Speed is adjusted using RAM's FSSPD(0x20) FSDELTA (0x21). Search Speed = 10mv/(128fs * FSSPD/FSDELTA) If FONcmd is received again during Play, Tracking/Sled is turned off.
58
DATA SHEET
S5L9250B
Related Memory Name FONbuf FSSPD FSDELTA FSCNT FSCNTmax FSCNTmin tFSCNT FEfs FEok_lvl FEpi_lvl FE Address 001B 0020 0021 0022 0028 0029 002D 002E 002F 0030 0062 Focus Search speed Focus Search delta Focus Search counter Focus Search output max Focus Search output min search wait time |FE| for focus pull-in FE ok level for Focus search FE pull-in level Focus error 0 x 1000 0 x 0400 0 x 1800 0 x E800 0 x 2000 Function Focus ON command buffer Data Value
Operation Description When the Focus On command is input, Delta waves are output from FOD as shown in the figure below. When to execute (UP/DOWN) Pull-in is decided according to the FON at this time. Search Speed or the slope is decided by the FSSPD and FSDELTA value, and the upper and lower limit duration is determined by tFSCNT. Also, PIM decides whether to have the FE recognition, pull-in level at the absolute value or the FEPK percentage.
FONU(Focus pull-in when actuator up) = 1 [FSCNTmax]
FONU (Focus pull-in when actuator up) = 0 [FSCNTmax] fod [tFSCNT]
fod
[tFSCNT]
[FSCNTmin]
[FEok_lvl] or FEPK]*[kFEok FEpi_lvl] or FEPK]*[kFEpi]
[FEpi_lvl] or [FEPK]*[kFEpi] [FEok_lvl] or [FEPK]*[kFEok
[FSCNTmin]
SENSE
SENSE
59
S5L9250B
DATA SHEET
Focus Pull-in Block Diagram
Delta Wave Output Block FE 11 fs
1
Vref FOD DAC 18
FEI
Focus Loop Filter
2
60
DATA SHEET
S5L9250B
TRACKING BALANCE Summary The purpose of this adjustment is for the average of the MAX and MIN values of each TE zero cross component's cycle, caused by eccentricity in the Off Track state, to be the same as Tofst. For CDs, TBAL signal is output and the E,F AMP gain within the RF AMP is modulated to repeat adjust the Balance. Command TBAcmd (0X0F00) : The command averages the MAX and MIN values of TE when Focus is on and Tracking is off, by using eccentricity. It must always be executed before going into Play (Tracking on). Code 0F D7 0 D6 0 D5 0 D4 0 1'st byte D3 PIM D2 0 D1 0 D0 TTBA
TIGAB: (D7 Reserved). Tracking input gain adjustment selection bit. 0 : Adjusted by MICOM. 1 : Tracking input gain changed by Servo according to TE level. TTBA: Test mode for TBA 0 : Normal TBA 1 : Tracking Balance is changed once, then reverted to previous mode, regardless of Tracking Balance OK. Related Memory Name TBALnoise Tengh fmin fmax TBok tTBALmax nTbal TBwt TBk Address 00C6 00C7 00CA 00CB 00CC 00CD 00CE 00CF FE6F Function zero cross noise level TEpeak enough level MINIMUM FREQUNCY for TZC detection MAXIMUM FREQUNCY for TZC detection T_BAL OK LEVEL (deviance allowed) No zero cross max time Period of one measurement Wait time after TBAL change, until the beginning of the re-measurement T_BAL adjustment sensitivity coefficient Data 0400 2000 00F6 0020 0100 2000 0008 0200 9000 8 periods 5.734ms -0.875 725Hz 5580Hz 19.5mV Value
61
S5L9250B
DATA SHEET
Detailed Operation Description Out of the periods of TE(tzc) signals passing through Vref and satisfying the conditions of fmin and fmax, TEmin, TEmax, and the median of the two values is determined. When these periods have continued nTbal times, the difference between the median value and the average adjustment level (=Tofst) is found to be the balance error. If the error is smaller than TBok, the adjustment is terminated, and if larger, multiply TBk to Tbal's previous value for output. So when the Tbal value has been output once, the Gain or Delay within the RF's TE AMP is varied, and the TE signal's balance error is varied as well. Because of this characteristic, you need a wait time (TBwt) longer than the settling time. When the system is stabilized, the above steps are repeated to get more balance error data.
TBwt TMAX
nTbal = 2
Tofst Vref
1 2 1 2
TMIN fmin measuring area fmax
Monitor Memory Name TEmax TEmin WORK0 Tbal Addr. 00C9 00C8 008B 00C5 Function TOP PEAK REG. BOTTOM PEAK REG. [TEmin+TEmax]/nTbal calculation results register Tbal output
Tracking Balance Block Diagram
E TE x(-N) F 3B TE AMP TinG fs
+
Tofst
TEin
Track Loop Filter
TRD
Balance Err Operation Block 3 RF IC Serial Data
62
DATA SHEET
S5L9250B
FOCUS BIAS Summary The purpose of adjusting the Focus Bias is to insure optimum RF signal quality during PLAY. Although it is the Jitter amount that shows RF signal quality, it is very difficult to actually measure the jitter on the IC and create an algorithm to find the point of minimum jitter. The alternative is to adjust the Focus Bias so that the envelope size is at its maximum. The RF signal has the characteristic of having the least jitter near the point of Focus Bias when the RF envelope size is at its maximum. Input signal : FE, RFENV Output signal : FOD Command FBAcmd (0x11 00) : When the RF signal is at its maximum, end Focus Balance Adjust using the RF Envelope signal. Always use after Focus pull-in. Code 11 D7 0 D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 TFBA
TFBA : Test mode for FBA. 0 : Normal FBA. 1 : Execute Focus Balance once then revert to previous mode, without regard to Focus Balance OK. Related Memory Name tFBacc FBdx FBlevel FBok FBIAS Address 00D0 00D1 00D2 00D3 0097 Function Disturbance Width BIAS increase/decrease amount Buffer Disturbance Level Bias OK Level fbias data save Data 05EA 0080 1000 0100 Value 8.58ms 9.8mV 312.5mV 19.5mV
63
S5L9250B
DATA SHEET
Detailed Operation Description The difference between the RFENV must be minimized by adding DISTURBANCE to the FE signal. This DISTURBANCE uses FE as standard and sets a LEVEL for its use. The DISTURBANCE Level value is set to the initial - direction, RFenv(-) value is stored, and put on HOLD for the WIDTH. The value is then given to the + direction, the RFenv(+) value is stored, the difference between the two values is found, and checked to see if it is in the FBok Level. Depending on whether the difference is (+) or (-), the dxbuf amount is subtracted from the Fbias amount to make the final Fbias value.
RFRP FBok
FOD FBlevel
FBdx
FBIA S
tFBacc
Monitor Memory Name Work0 Work1 Work2 Focus Bias Block Diagram Address 0089 008a 008b Minus Rfrp Reg. Plus Rfrp Reg. Work1-Work0 Calculation results register Function
FE (from RF)
FinG
x(-N)
FE fs
+
+
FEin
Focus Loop Filter
FOD
FiG RFRP (from RF) fs/16 RFENV Avrg Filter RF_ENV
Fofst
Fbias
Focus BIAS Err operator Filter
64
DATA SHEET
S5L9250B
TRACKING PULL-IN Summary Tracking Loop is turned On using TZC Frequency when the Tracking On Command(0X03) is received in Off Track status. Input signal : TE Output signal : TRD Command : Tracking Pull-in command. If tracking is already on when this command is received, no further actions are taken. Code 03 D7 0 TON : Track On/Off. 0 : Off. 1 : On. SLDX : Sled Servo On/Off. 0 : SLED off. 1 : Sled servo on after a set time period since Tracking on. TFSB : Eccentricity compensation pull-in control bit during Track pull-in. 0 : Normal pull-in. 1 : Eccentricity Compensation pull-in (between the edges of TZC are counted and pull-in is executed where the frequency is low). TOLB1 - 0 : Lens Brake during Track Pull-in. T/F Gain control enable/disable. Used when executing pull-in after a jump using the Stepping motor. 0X : OFF. 10 : ON (lens kick value used for lens brake time during Normal Pull-in). 11 : ON (Pull-in after Stepping motor feed kick). KICK : KICKsignal control (for stepping motor sled move). 0 : Set KICKsignal to "L". 1 : Set KICKsignal to"H". D6 TON D5 SLDX D4 TFSB 1'st byte D3 D2 D1 0 D0 KICK TOLB1 0
Related Memory Name tTpiH tTpiL Address 004A 004B Function minimum TZC time when Tpi maximum TZC time when Tpi Data 0800 2000 Value 2048*0.1 us 8192*0.1 us
65
S5L9250B
DATA SHEET
Operation Description 1) TFSB = 0 When the Tracking On command is input, the MIRR and TZCsignal are checked. When a TZC edge is generated while the MIRR signal is "L", tracking is assumed to be on, and sense is output as "H". 2) TFSB = 1 When TZC period is less than tTpiH but larger than tTpiL, and a TZC edge is generated when MIRR signal is "L", tracking is assumed to be on, and sense is output as "H".
tTpiH> tTpiL<
TE
TZC Mirr
SENSE
66
DATA SHEET
S5L9250B
LOOP GAIN Summary The Loop Filter's Gain is automatically adjusted so that the Open Loop Bandwith for Focus/Tracking is at the specified frequency needed in the system. Input signal : FE, TE Output signal : FOD, TRD
nsk adjustment Gain (open loop)
initial state
fc
freq. adjustment goal
Command Focusing Gain Adjustment command (FGAcmd (0X0C00)) : This command adjusts the Auto Focus Gain. Use when the Focus servo is on, and the tracking servo is either on or off. Code 0C D7 FGud D6 0 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 TFGA
FGud : Auto Focus Gain Update. 0 : No update. 1 : When changing Kfo, Kfuo after automatic adjustment, update according to the rate of change during the automatic adjustment. TFGA : Test mode for FGA. 0 : Normal FGA. 1 : Change Focus Gain once then revert to previous mode, regardless of Focus Gain OK.
67
S5L9250B
DATA SHEET
Tracking Gain Adjustment command (TGAcmd (0X0D00)) : This command adjusts the Auto Tracking Gain. Use when Focus servo and tracking servo are on.
Code 0D D7 TGud D6 0 D5 0 D4 0
1'st byte D3 0 D2 0 D1 0 D0 TFGA
TGud : Auto Tracking Gain Update. 0 : No update. 1 : When changing Kto, Ktuo after automatic adjustment, update according to the rate of change during the automatic adjustment. TTGA : Test mode for TGA. 0 : Normal TGA. 1 : Change tracking gain once then revert to previous mode, without regard to Tracking Gain OK. Related Memory Name Gin GDF1 Gout Ydata zYdata SINdata sTsz sHsz Xwave xGwait xGcnt Xdisturb Xphase Ffrq/Tfrq FGok/TGok Kf/Kt Kcf/Kct FGmax/TGmax FGmin/TGmin Address 0050 0051 0052 0053 0054 0055 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00EC/00E9 00EA/00E7 FE8C/FE84 FE8D/FE85 0058/0056 0059/0057 Function input for gain adjust BPF data for Gain adjust BPF out Ydata=X+2Z Ydata(n-1) sin data total sindata size sTsz/2 current sin data pointer Wait Time measurement period disturb data phase error Focusing/Tracking Bandwidth Focusing/Tracking Gain Ok Level Focusing/Tracking Disturbance Level Focusing/Tracking adjustment sensitivity coefficient Focus/Track Gain Maximum Value Focus/Track Gain Minimum Value 0009/000C 0005/0005 0500/0400 E000/0800 E000/1000 F500/0400 1.8K/2.4K 0.38 AE 71.7/78.1mV -0.25/0.063 -0.25/0.125 -0.086/0.032 0008 0010 8 periods 16 periods Data Value
68
DATA SHEET
S5L9250B
Detailed Operation Description The adjustment consists of outputting a sine wave to the FOD output, comparing the original sine wave and the signal that has passed through MECHs such as P/U to make the phase difference into 90. The LOOP EQ FILTER's final output gain is automatically adjusted. The adjustment is repeated many times to reach the optimum state. To eliminate NOISE components in the input signal, the signal goes through BPF handling.
2 fc fs
BPF Configuration and Filter Coefficient
Gin
kfga0
+ +
Gout Z-1 kfga3
Z-1 kfga1 kfga2
Name Kfga0/Ktga0 Kfga1/Ktga1 Kfga2/Ktga2 Kfga3/Ktga3
Address FF88/FF80 FF89/FF81 FF8A/FF82 FF8B/FF83
Function Coefficient for adjusting GAIN POLE FILTER 1 coefficient ZERO FILTER coefficient POLE FILTER 2 coefficient
Data 0FAC/16A3 7829/74AE 8000/8000 7829/74AE
69
S5L9250B
DATA SHEET
Phase Difference Detection Waveform
Y=xGdata
STsz 2
0
-
+
STsz X=sine(fc) |-|< |+| ae small Gain
Zero Cross |-|>|+| large Gain c
TE xGwait xGcnt xGok Phase adjustment goal nsk up
Loop Gain Block Diagram
SINE XinG FE/TE
x(-N)
X + fs Xofst XEin Z +
fc
Focus/Tracking Loop Filter * nsk FOD TRD In the disgram, X stands for F(focus) or T(tracking).
(from RF)
Xwave + (fc) Y BPF DTx XGA Phase err operater
XiG
70
DATA SHEET
S5L9250B
VELOCITY CONTROL TRACK JUMP Summary Velocity control Track jump uses the MIRR signal generated from the TRACK ERROR signal (TZC) read from the disc during jump and the RFRP signal to detect the P/U's velocity and direction. It uses the difference between the previously designated velocity profile and the actual velocity to output kick/brake to TRD, controlling track jump. Input signal : TE(TZC), MIRR Output signal : TRD, SLED0, SLED1, SENSE Command (0x05XX) TRack Jump command (TRJcmd) : TRJcmd is a Track jump command that is used for track kick/brake jump and track velocity control jump. Code 05 D7 DIR DIR : Direction you wish to move in using the Track Counter (TC). 0 : Outward movement. 1 : Inward movement. NUMS : Number of upper tracks you want to move (0x00 - 0x7F). Lower Jump track number is designated by CJNCcmd(0B). Cd Jump Number Common command (CJNCcmd) :This command designates the track number of TRJcmd and RPTcmd(Reserved), and the lower track number of SMVcmd, PSJcmd(Reserved), and STEPcmd(Reserved). Code 0B D7 D6 D5 D4 NUMS NUMS : The number of lower tracks you want to move (0x01 - 0xFF). 2nd byte D3 D2 D1 D0 D6 D5 D4 1'st byte D3 NUMS D2 D1 D0
71
S5L9250B
DATA SHEET
Jump MoDe1 select command (JMD1cmd) : JMD1cmd is a Jump-related initial value selection command. Code 18 D7 JCKS1-0 D6 D5 0 D4 0 1'st byte D3 0 D2 0 D1 0 D0 0
JCKS1-0 : H/W counter clock selection bit during Jump. 00 : MIRR 01 : TZC 1X : Latched MIRR (initial value). Jump MoDe4 select command (JMD4cmd) : JMD4cmd is a Jump-related initial value selection command. Code 1B D15 RVSB D14 VCMP D13 VEDG 1'st byte D12 D11 VPRDR D10 D9 VCLKS D8
RVSB : Reverse check control during Jump. 0 : If there is less tracks than RVSnum(0xbe) during reverse, jump stop. 1 : Do not execute Reverse check. VCMP : 1 Counter compensation (when Cout is "H"). 0 : Do not Compensate. 1 : Compensate. VEDG : Velocity jump period counter standard edge selection. 00 : Falling & Rising 01 : Falling 10 : Rising 11 : Falling & Rising VPRDR : Velocity jump period standard signal (H/W counter and Kick/Brake standard clk changes together as well). 00 : TZC 01 : MIRR 10 : L_TZC (L_MIRR is selected for H/W counter and Kick/Brake standard clk). 11 : L_MIRR VCLKS : Velocity Clock Select 00 : CK32 (1.25MHz = 800ns) 01 : CK16( 2.5MHz = 400ns) 10 : CK08( 5MHz = 200ns) 11 : CK04( 10MHz = 100ns)
72
DATA SHEET
S5L9250B
Related Memory Name tBRK1 tBRK Tstbl Twin NUMS Vkick Rtrk Vtmp Vctl King VTKp VTKm TMedge KICKedge RVSnum Jnum tJnoise JMPCMDbuf JMPDATAbuf Jcomp tLBoS tGUpS tTGUpS Address 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7 00B8 00B9 00BA 00BB 00BC 00BD 00BE 00BF 00C0 004C 004D 00F3 00DA 00DB 00DC Function brake time for 1 track jump brake time for upper 1 track jump stable time after jump Track Jump TZC blind Time jump track number initial kick level for velocity jump residual track number([vNUMS]-H/W counter-Vcmp) center calculation value memory accumulation value of difference between current and profile velocity Velocity error plus kick for velocity control jump minus kick for velocity control jump edge counter velocity control start edge Reverse jump check minimum track number Number of tracks jumped (for stepping motor sled move) te zero cross noise cancel Jump command save buffer Jump data save buffer compensation for jump lens brake time F gain up time T gain up time 500 300 3A9 2 2000 E000 Data 18 C 0 0x10 90s Value
73
S5L9250B
DATA SHEET
TM_max TM_WIN
TE
V_kick
TRD
tLBoS
tGUpS tTGUpS
SLED0,SLED1
SL_avrg Vref
KICK SENSE
BPROf0 - e : velocity profile REVCF0 - e : velocity profile error compensation factor The error compensation factor is different according to the velocity. ( 5kHz : You must multiply the error compensation factor that is appropriate for 10kHz. If the error compensation factor of 5kHz is 0.5, the error compensation value of 10kHz is considered to be 1.) Velocity Control Related Block Diagram
TRbrk(S/W) TEin VPE Tracking Loop Filter for anti-aliasing TRDLEO LPF Sled Loop Filter SLDOUT DAC SLED1
20 21
TE
9
fs
TRD
17
fs/16 RFRP RFCT TZCA
+ + -
Velocity control output block SLDIN MIRR Movement speed + Speed campensation factor detect track count TZC reverse check -
SLED0
Vref
Velocity profile
74
DATA SHEET
S5L9250B
Operation Description Jump-related values are adjusted before executing velocity jump. For example, the window time ([TM_WIN]) is selected in order to eliminate errors caused by MiRR or TZC noise early in the jump. Also, values such as lens brake time ([tLBOS]), focus gain up time ([tTGUS]), and tracking gain up time ([tTGUDS]) are selected after the jump. If needed, the initial kick values ([VKP],[VKM]) must be set as well. Values such as clock and kick/brake period, which are used as standards during jump, are first set by 1Bcmd. The number of tracks you want to jump are input through the velocity jump command (0x5, 0x0B). Also, the velocity profile that fits the clock is input into BProf0 - BProfe before the jump. The default value is the velocity profile data that executes kick/brake for each period. When initialization is over, the jump is executed. The value that is output as trd is the result from the velocity profile [Prof0-e] and the L_MIRR positive edge's counter value difference signal that has been sent through the loop filter. Name RVECF0 RVECFe BProf0 BProfe Prof0 - Profe kVHL IVBL1 IVBL Jperiod kVf Address FEC0 FECE FED0 FEDE 1E0 - 1EE FECF FEDF FEEF 172 FEF3 Function Error's comparative velocity compensation value Basic velocity profile data Data 4000,4000,4000,4000,40 00,5000,6000,7FFF 00FA,00FA,00FA,00FA, 00FA,00D2,009A,0070 * One period of VCLKS Value
Velocity profile data used in the actual jump (variable according to command) Last brake Level in upper 1 track jump Initial Velocity Brake Level in 1 track Initial Velocity Brake Level in upper 1 track Jump period for RPTcmd % for velocity controlled track jump 4000 50% 2000 3.125 V
75
S5L9250B
DATA SHEET
VELOCITY CONTROL FEED MOVE Summary Velocity control feed move detects moving speed and direction of P/U by using the TRACK ERROR signal (TZC) read from the disc and the MIRR signal generated from the RFRP signal (deferent of RF signal's peak to peak level). It executes track jump use by the difference between the previously designated velocity profile and the actual velocity to output kick/brake to TRD. Input signal : TE(TZC), MIRR Output signal : TRD, SLED0, SLED1, SENSE Command : transmit 3 command JMD2cmd (0x19hh) : Set jump-related mode Code 19 D7 LFKS D6 FKMOD D5 FSEQ D4 FNEQ 1'st byte D3 HYS D2 TGS D1 FDC D0 -
LFKS: Lens kick / Feed move select bit. 0: Lens kick. 1: Feed move. FKMOD: When LFKS is 'H', feed move type select. 0: Speed feedback type feed move. 1: Open control type feed move. FSEQ: Usage feed search EQ in feed move. 0: Do not use 1: Use feed search EQ FNEQ: Usage feed normal EQ in feed move. 0: Do not use 1: Use feed normal EQ HYS: Usage hysterisis in the end of search. 0: Do not use 1: Use hysterisis TGS: Usage tracking gain up in the end of search . 0: Do not use 1: Use tracking gain up FDC: Add initial kick value(offset) to feed output in feed move . 0: Do not add 1: Add
76
DATA SHEET
S5L9250B
VCFcmd (0x06hh): Select Velocity control feedkick jump direction and upper track number. Code 06 D7 B/F D6 D5 D4 1st byte D3 D2 D1 D0
Upper byte of jump track
B/F: Select move direction in kick. 0: Backward 1: Forward
CJNCcmd (0x0Bhh): Set jump-related mode. Code 0B D7 D6 D5 D4 1st byte D3 D2 D1 D0
Lower byte of jump track
NUMS : The range of tracks number you want to move is 1-215(32767).
JMD3cmd (0x1Ahh): Select lower track number Code 1A D7 0 D6 0 D5 0 D4 0 1'st byte D3 HCRE D2 HCRC D1 D0 HCRS
HCRE: Hardware counter reference edge. 0: Raising 1: Falling HCRC: Hardware counter reference clock. 00: CK32(1.25MHz = 800ns) 01: CK16( 2.5MHz = 400ns) 10: CK08( 5MHz = 200ns) 11: CK04( 10MHz = 100ns) HCRS: Hardware counter reference signal. 0: TZC. 1: Mirr.
77
S5L9250B
DATA SHEET
Related Memory Name FLAGbuf FLABsav FLAGextral Cstrd Zstrd JUMCMDbuf JUMDATbuf JMD23buf FKWt FKPt FVGI FVGO Ctmp MAXV Vgab Vgen FINP Fgab Pre_cnt R_trk Cspd FEQ1 FEQ2 FEQ3 FEQ4 FEQ5 Fkpok Address 0014 0015 0016 008D 008E 0035 0036 001D 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 010A 010B 010C 010D 010E 010F 0110 0111 0112 Jump track number Current strd store Previous strd store Save jump command Save jump track number Save JMP2, JMP3 command(JMP2: upper, JMD3: lowder Kick initail window time Kick calculation period time 0x10 0xF Save FLAGbuf Function Flag mode( use only lower 4 bits) Data Value
78
DATA SHEET
S5L9250B
Name Kv10 Kv11 Kv12 Kv13 Kt1a Kv20 Kv21 Kv22 Kv23 Kv24 Kv25 Maxspd Prdspd Ttov Ht_tov Bpset INV_BP Mgraph Minspd Kvg1 Kvg2 Kvg3 Kvg4 Kvg5 Kvg6 Kvg7 Kvg8 Kvg9 Flim Kv2a BC_val
Address FF00 FF01 FF02 FF03 FF04 FF05 FF06 FF07 FF08 FF09 FF0A FF0B FF0C FF0D FF0E FF0F FF10 FF11 FF12 FF20 FF21 FF22 FF23 FF24 FF25 FF26 FF27 FF28 FF30 FF31 FF32 10MHz(100nS) Jump track number 5KHz 3-HCRC 4096 track 1/4096 shift 200KHz 11KHz Feedback search EQ Save jump track number
Function Velocity generator filter coefficient
Data 00A0 7B90 07D0 0000 0570 7F90 0250 7FA0 B370 4EB0 0147 0012
Value
Save JMP2, JMP3 command(JMP2: upper, JMD3: lower Kick initail window time Kick calculation period time
1000 0003 8 6000 5800 5000 4800 4000 3800 3000 2800 2000
Fc value decision constant
0050 E000 4000
79
S5L9250B
DATA SHEET
Velocity Profile Velocity profile can decide kick time, maximum move velocity, break point.
Convergence value(M) (1) Maximum move velocity (3) Kick time N tracks (2)
Kick time
Brake point
Brake point
Kick Time In graph(1), convergence track number is decide according to jump track, the time arrived around M is kick time. This is decided by LFS's fc Maximum Move Velocity Maximum Move velocity is decided by relation of convergence value(M) in graph(1) and N track in graph(2) Break Point Break point is decided by mixing of graph(1) and graph(2). Break point is the time changed the sign in comparison between value of graph(1) and value of graph(2).
Relation Of Track Number And Velocity When maximum move velocity is Max, processing period is P, convergence value in graph(1) is M, Maximum move velocity is Max Maximum track number in processing P is Max/P When convergence value is N, maximum move velocity is (M*Max)/N, maximum track number is (M*Max)/(N*P) Change of convergence value per 1 track is P*M/Max
80
DATA SHEET
S5L9250B
FOKB GENERATION Summary The FOCUS OK signal is generated from the E+Fsignal (SBAD) input from the RF IC. Input signal : SBAD Output signal : FOKB
FE < tFOKBLdly FOKBlvl SBAD > tFOKBHdly FOKf FOKB > tFOKBLdly
Command The operation is handled in units of fs/16 without a separate execution command. Related Registers Register FOKBlvl tFOKBHdly tFOKBLdly Address 0098 009A 009B FOK High Delay Time FOK Low Delay Time Function SBAD's FOCUS ON/OFF deciding LEVEL -> changes FOKf
81
S5L9250B
DATA SHEET
Focus/Tracking Loop Filter Configuration
Input
ki
k10
+
+
k15
+
+
k0
shl
Output
Z-1
k11 k12
Z-1
k13 k14
Z-1
k16
k20
+
k22
+
k24
+
Z-1
Anti-Aliasing Filter
k21
Z-1
1/16 Interrupt processing
k23 k25
Coeff Input FE TE
Ki
K10
K11
K12
K13
K14
K15
K16
K20
K21
K22
K23
K24
K25
Ko
shl
Kfi Kti
Kf10 Kf11 Kf12 Kf13 Kf14 Kf15 Kf16 Kf20 Kf21 Kf22 Kf23 Kf24 Kf25 Kt10 Kt11 Kt12 Kt13 Kt14 Kt15 Kt16 Kt20 Kt21 Kt22 Kt23 Kt24 Kt25
Kfo Kto
Kfshl Ktshl
Analog Block
VREFI
+
Gain control AMP
+
TE_AMP_OUT
10K
AMP4
TE TELPF
470K
AMP2
-
0 1
-
TEDFCT_en TIG[4:0]
SLT[4:0]
VREFI
+
Gain control AMP
+
FE_AMP_OUT
10K
AMP5
TE FELPF
470K
AMP3
-
0 1
-
FEDFCT_en FIG[4:0]
SLT[4:0]
82
DATA SHEET
S5L9250B
Analog Block
Analog Multiplexer VREFI vrefo TRD vrefo AMUX[1:0] Analog Multiplexer VREFI vrefo FOD vrefo AMUX[1:0] 20K VREF
-
A3 A2 A1 A0
VREFI RFRP SBAD
1000K TZCA VREFI
+
COMP
TZCO
ADin2
-
165K RFCT 2K RFRP
+
COMP
MIRR
-
Analog Multiplexer VREFI ADin1 A7 A6 A5 A4 A3 A2 A1 A0 SLT[2:0] ASEL[2:0] AOUT
A3 A2 A1 SBAD A0 ADin2 ADin1 ADin0 ADin0 TE_AMP_OUT FE_AMP_OUT RFRP
20K CEI
+
AMP
83
S5L9250B
DATA SHEET
CD-DSP
Characteristics

Wide capture range Analog PLL. Data Slicer that uses Duty Feedback method. EFM demodulation. Sync detection, protection, insertion. CLV, CAV DISC Spindle Motor control. C1/C2 ECC Built-in 16 K SRAM for ECC. Subcode P to W processing feature. CD-DA Audio processing feature. SUB-Q De-interleaving & CRC Check 4X or 8X CD-DA DATA transmission support to CD-ROM Decoder Block for Audio Buffering (subcode sync and CD-DA DATA's synchronous output). Subcode Buffering. Subcode Sync. Insertion, Protection
84
DATA SHEET
S5L9250B
Block Diagram
Data Slicer RF Signal
PLL (Bit Clock Regenerator)
EFM (Demodulator & Sync Detector)
Spindle Control
SPINDLE
ECC SRAM
MEMORY Control
PSC CMD TIMING signal MICOM I/F
C1/C2 ECC SUBCODE Handling Analog Audio D/Filter & 1-bit DAC AUDIO Handling SUB-Q Handling DSP I/F SUBCODE I/F
MICOM I/F
Digital Audio Handling
Digital Audio Out
SBCK, SUBD, SCOR Nx-to-1X LRCK, ADATA, BCK Audio Data
85
S5L9250B
DATA SHEET
Register Map 1) Write Register
NAME
INTCTL SYSCONT SYSINIT MONCON HDDLYCTL EQVSET JITCTL
Addr.
40h 41h 42h 43h 44h 45h 46h
BIT7
SBQIEN CLKSEL -
BIT6
REVIEN MRESET
BIT5
ROVIEN MUTE -
BIT4
JITIEN CDROM -
BIT3
-
BIT2
S16T24B -
BIT1
ZCMT EFML_EN
BIT0
RAMCLR PLCK_EN
SLORL[1:0]
EFMORP[1:0] VHD_DLY[3:0]
EHD_DLY[3:0] EQV_SET[6:0]
PHOLD_E X DLY_SEL[1:0] KICKEN
AUDRST_ EN
MPVCO
MPEQ
-
SERCTL AUDCTL
47h 48h
DEEM_EN
EMSEL SCSELP
SCSEL PLCK_WI NS
EQ_SPD[3:0] SUBDENS EL OFC2 SYNCSEL -
CLK_SV AUDRST
ECCCTRL0 ECCCTRL1
49h 4Ah
ERAMOD JUMPEN
C1FLG MRESYNE N
C2FLG JITTEREN
C2PSEL
C2ECC
C2-FGTYPE[3:0]
DFCTCTL SBSY
4Bh 4C
DSHD SS0WSE L
EQHD SS1WSEL
SLON SS0WND RST
SS1WND RST
SS0ISEL[1:0] SS1ISEL[1:0]
DAOSUB PLLCTRL0 PLLCTRL1 PLLCTRL2 PLLCTRL3 PLLCTRL4 PLLCTRL5 SLICTRL0 SLICTRL1 SLICTRL2 EFMCTRL1
4D 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah LPFS TSLCS SUBCON EQFIX SBFLUSH EN RES[2:0] PKEN SSEL TMX1 PLOCKSET[1:0] TMX0 PDHD
M2DSUBCODE[7:0] SLPD1 SLPD0 UPDN[1:0] TALGC VCOFIX FDGAIN[7:0] PWM[7:0] SLFIX[6:0] SLEN PKCTL WSEL1 DFRL[2:0] WSEL0 GSEL[1:0] INLG[2:0] VCOHD SLEFM
iDACp[5:0] iDACn[5:0]
EFMCTRL2
5Bh
-
CK33MSE L
-
-
-
-
GFSDET
WNDRST
MTRCTRL FCSEL
5Ch 5Dh
LJUMP FPLUS
LOCKEX ULHD
MON_EX FAGD
DCTL RCAV FNCW[1:0]
SPD[3:0] FCW[1:0]
86
DATA SHEET
S5L9250B
NAME
PCSEL PCOFFS EMOSEL CAVSEL1 CAVSEL2 DAOCTRL CAVCTRL1 DACCTRL
Addr.
5Eh 5Fh 60h 61h 62h 63h 64h 66h
BIT7
BIT6
BIT5
FGWDT
BIT4
MOTSEL
BIT3
PCEN
BIT2
PCR
BIT1
BIT0
FGSEL[1:0]
PCW[1:0]
POFFS[7:0] CLVHD CAVCK2 SMON1 CAVCK1 SMON0 CAVCK0 SPOLAR CAVR[7:0] DAOEN ROTSEL DN SDACCK ROVS[2:0] PWRSAV E MEMPHIN MDAOUIN COPYEN EMPHEN ACMODE KICK BRAKE PWMCA[1:0] CAVR[9:8]
RIS[1:0] MUTEL PDL
FAL[1:0] DEEM
DATTN
67h
-
-
ATTL[5:0]
2) Read Register
NAME INTSTAT FRAME COUNTER Addr. 70h 71h 72h 73h 74h 75h SUBQ DATA 76h 77h 78h 79h 7Ah 7Bh 7Ch C1EBYTE C1ECODE DPSTAT C2EBYTE C2ECODE RBC RBC WBC WBC 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h BIT7 SUQINT FC15 FC7 CTL3 TNO7 INDEX7 MIN7 SEC7 FRM7 ZERO AMIN7 ASEC7 AFRM7
C1EBYTE8 C1EBYTE0
BIT6 REVINT FC14 FC6 CTL2 TNO6 INDEX6 MIN6 SEC6 FRM6 ZERO AMIN6 ASEC6 AFRM6
C1EBYTE7 C1ECODE6
BIT5 ROVINT FC13 FC5 CTL1 TNO5 INDEX5 MIN5 SEC5 FRM5 ZERO AMIN5 ASEC5 AFRM5
C1EBYTE6 C1ECODE5
BIT4 JITINT FC12 FC4 CTL0 TNO4 INDEX4 MIN4 SEC4 FRM4 ZERO AMIN4 ASEC4 AFRM4
C1EBYTE5 C1ECODE4
BIT3 FC11 FC3 ADR3 TNO3 INDEX3 MIN3 SEC3 FRM3 ZERO AMIN3 ASEC3 AFRM3
C1EBYTE4 C1ECODE3
BIT2 FC10 FC2 ADR2 TNO2 INDEX2 MIN2 SEC2 FRM2 ZERO AMIN2 ASEC2 AFRM2
C1EBYTE3 C1ECODE2
BIT1 FC9 FC1 ADR1 TNO1 INDEX1 MIN1 SEC1 FRM1 ZERO AMIN1 ASEC1 AFRM1
C1EBYTE2 C1ECODE1
BIT0 FC8 FC0 ADR0 TNO0 INDEX0 MIN0 SEC0 FRM0 ZERO AMIN0 ASEC0 AFRM0
C1EBYTE1 C1ECODE0
SBQERR
C2EBYTE8 C2EBYTE0
C2EBYTE7 C2ECODE6
C2EBYTE6 C2ECODE5
C2EBYTE5 C2ECODE4
C2EBYTE4 C2ECODE3
C2EBYTE3 C2ECODE2
C2EBYTE2 C2ECODE1
C2EBYTE1 C2ECODE0
RBC7 WBC7
RBC6 WBC6
RBC5 WBC5
RBC4 WBC4
RBC11 RBC3 WBC11 WBC3
RBC10 RBC2 WBC10 WBC2
RBC9 RBC1 WBC9 WBC1
RBC8 RBC0 WBC8 WBC0
87
S5L9250B
DATA SHEET
I/O DEFINITION CLV-related signal (MOTOR I/F) Symbol SPINDLE I/O O Description AFC/APC output, PWM (H, L, Hi-z)
PLL-related signal Symbol VCTRL RVCO RDAC VALGC RISS PWMO PWMI I/O I B B I O O I Description VCO Control Voltage VCO V/I Converting Resistor Biasing Resistor for iDAC at Charge Pump ALGC PWM LPF OUTPUT VCO BIAS Resistance ALGC Carrier Frequency controlling output ALGC Carrier Frequency controlling input comment for one-chip
Slicer & EQ-related signal Symbol RFI EFMCOMP EFMSL LPF0 LPF1 EQCTL I/O I O O I I O Description Eye Pattern from RF Duty Feedback Slicer output Duty Feedback Slicer, slicer output LPF input ( CD 1X, 4X, 8X,16X) LPF input (CD X24, 24X,32X, 40X, 48X) EQ output current comment for one-chip
EFM Demodulation-related signal Symbol GFS I/O O Description "H" when detected Frame Sync and inserted Frame Sync coincide comment for one-chip
88
DATA SHEET
S5L9250B
Subcode I/F-related signal Symbol EXCK SBSO WFCKO SCORO I/O I O O O Description Subcode Data Readout Clock Subcode P to W serial output Delayed WFCK (Write Frame Clock) When either S0 or S1 is detected, SCORO is high comment for one-chip
1-Bit DAC and Audio Handling-related signal Symbol LRCKI I/O I Description Sample Rate Clock Input comment for one-chip From interpolation or ATAPI controller (or external input PAD)
BCKI SDATAI Vref AoutR AoutL VSSA VDDA C2PO LRCKO BCKO SDATAO
I I I/O O O G P O O O O
Bit Clock Input Serial Digital Input Data Reference Voltage Output for Bypass Analog Output for R-CH Analog Output for L-CH Analog Ground Analog Power Supply C2 error pointer Sample Rate Clock Output Bit Clock Output Serial Digital Output Data for external interface output PAD PAD PAD PAD Analog Power PAD for post analog-filter
89
S5L9250B
DATA SHEET
General MICOM Register 1) Write Register 40h INCTL Reset value B7 SBQIEN 0 B6 REVIEN 0 B5 ROVIEN 0 B4 JITIEN 0 B3 B2 B1 B0 -
The INCTL Register controls the Data Processor Part's Interrupt generation. In other words, it has the ability to control the SINTB (PIN56)'s Interrupt output signal regardless of whether an Interrupt has been generated within the chip. If you enable this register's bits, the appropriate interrupts are output through Pin 56. If you disable the bits, the output of the interrupt signal is prevented. The interrupt that is received and handled from Firmware is the SUB-Q Interrupt controlled by SBQIEN (Bit 7). Firmware is aware of the chip's current condition by reading SUB-Q DATA 10 Bytes (73h - 7Ch). Bit7 - SBQIEN : CD Subcode-sync Interrupt Request Enable Enable/Disable bit of the Subcode-sync Interrupt generated every 98 frames at the CD DASP (13.3 ms at 1x). 1 : Enable 0 : Disable Bit6 - REVIEN : Enable/Disable bit of the REVINT Interrupt generated at each disc rotation during reverse motion. 1 : Enable 0 : Disable Bit5 - ROVIEN : Enable/Disable bit of the ROVINT Interrupt generated at each disc rotation when the motor's rotation speed exceeds that designated by MICOM Register CAVCTL2.ROVS[2:0](64h.6-4) 1 : Enable 0 : Disable Bit4 - JITIEN : Enable/Disable bit of the Jitter Interrupt generated when there is jitter in the Memory Control Block. 1 : Enable 0 : Disable
90
DATA SHEET
S5L9250B
40h SYSCONT Reset value
B7 CLKSEL 1
B6 -
B5 MUTE 1
B4 CDROM 1
B3 -
B2 S16T24B 1
B1 ZCMT 0
B0 -
The SYSCONT Register carries out the general control of the Data Processor. Bit7 : CLKSEL : Clock Selection Bit 1 : Use PLCK Clock (4.3218 MHz * n speed ratio) when transmitting and handling CD-DA, V/CD, and CD-ROM's ECC. 0 : Use X'tal Clock when transmitting and handling CD-DA and V/CD's ECC (MAX 8x). Use PLCK Clock when exceeding 8x. Bit5 : MUTE : Mute Control Bit. After Reset, the initial state is Mute ON. Firmware must release the Mute after system is stabilized. 1 : Mute ON. 0 : Mute OFF (normal status). Bit4 - CDROM : Disc Selection Bit. This bit controls Interpolation. Interpolation can only be carried out in "L" status in CD-DA Mode . 1 : CD-ROM or Video-CD Mode (INTERPOLATION OFF). 0 : CD-DA Mode (INTERPOLATION ON). Bit2 - S16T24B : CD-DASP output Format Control Bit. 1 : 32-Bit Slot Out (Toshiba 16-Bit Mode). 0 : 48-Bit Slot Out (Sony 24-Bit Mode). Bit1 - ZCMT : ZERO-CROSS Mute Control Bit. 1 : Zero Cross Mute ON. 0 : Zero Cross Mute OFF. 42h SYSINIT Reset value B7 B6 MRESET 1 B5 B4 B3 B2 B1 B0 RAMCLR 1
The SYSINIT Register initializes the Data Processor's system. Bit6 : MRESET : MICOM Master Reset. Only the Chip is reset by MICOM. A period of time after Reset ON (more than 10 us), the chip automatically turns off the Reset. 1 : Reset OFF. Normal operation mode. 0 : Reset ON. Bit0 - RAMCLR : SRAM Clear bit for use of ECC. The RAMCLR bit is "H" after Power-on Reset, and writes initial value "FF" on the ECC SRAM. S5L9250B clears all ECC SRAMs, makes the RAMCLR Bit into "L", and starts the Main operation. 1 : Enable ECC SRAM Clear. 0 : Disable ECC SRAM Clear.
91
S5L9250B
DATA SHEET
MONCON : Monitor Output Control Register Address 43 H Reset value bit7 SLORL1 0 bit6 SLORL0 0 bit5 0 bit4 0 bit3 bit2 bit1 0 bit0 0
EFMORP1 EFMORP0
EFML_EN PLCK_EN
Bit7 to 6 - SLORL[1:0] : P81 Monitoring Output Selection signal EFMORP1 0 0 1 1 EFMORP0 0 1 0 1 EFMSL (Slicer) EFML (PLL) WFCK PAD 81 Output PEAK (Slicer detected Defect)
Bit5 to 4 - EFMORP[1:0] : P78 Monitoring Output Selection signal EFMORP1 0 0 1 1 EFMORP0 0 1 0 1 PAD 78 Output 0 0 PLCK RFCK
* For using Pin78 to output pin, DAOCTRL.MEMPHIN(63h.3) is have to set "L" Bit1 - EFML_EN : PLL Block EFML Monitor signal output ENABLE Bit (H Active). Bit0 - PLCK_EN : PLL BLOCK PLCK Monitor signal output ENABLE Bit (H Active).
92
DATA SHEET
S5L9250B
HDDLYCTL : HOLD TIME DELAY Control Register Address 44 H Reset value bit7
VHD_DLY3
bit6 0
bit5 0
bit4 0
bit3 0
bit2 0
bit1 0
bit0
EHD_DLY0
VHD_DLY2 VHD_DLY1
VHD_DLY0 EHD_DLY3
EHD_DLY2 EHD_DLY1
0
1
Bit7 to 4 - VHD_DLY[3:0] : After JUMP signal is generated, the VCO HOLD TIME is delayed in 16 stages in units of 30 us from 0 420 us according to the VHD_DLY[3:0] value. (JUMP = ATSC + KICK + DFCT from Servo) O Refer to 46h Register Description for Td us-related descriptions .
PHOLD PHOLD_VCO
Change from 0u - Td us by VHD_DLY[3:0]
Bit3 to 0 - EHD_DLY[3:0] : After JUMP signal is generated, PLL is LOCKED when SLICTRL2.EQNORDL Bit(59h.1) is "H", then the EQ_HOLD signal is delayed in 16 stages in units of 30 us from 0 ~ 420 us according to the VHD_DLY[3:0] value. (JUMP = ATSC + KICK + DFCT from Servo)
PHOLD PHOLD_EQ
Change in Td us by EHD_DLY[3:0]
EQVSET : EQ Control Voltage Register (R/W for TEST) Address 45 H Reset value bit7 bit6 1 bit5 0 bit4 0 bit3 0 bit2 0 bit1 0 bit0 0
EQVSET6 EQVSET5 EQVSET4 EQVSET3 EQVSET2 EQVSET1 EQVSET0
Bit6 to 0 - EQVSET[6:0] : When a Long Jump is executed in CAV Mode from an inner disc circumference to an outer circumference, the PLL and EQ blocks can quickly react by MICOM writing the Equalizer control voltage value in EQVSET[6:0] after the jump. MICOM must write the EQVSET value before the Long Jump and set the MTRCTRL.LJUMP(5Ch.7) Bit to "H". The EQ Controller outputs the EQVSET[6:0] value as EQCTL(Pin 128) only while the EQ_HOLD (refer to 4Bh) is being generated while the LJUMP Bit is "H". At all other times, the EQ voltage controller's voltage is output.
93
S5L9250B
DATA SHEET
JITCTL : Jitter Control Mask Register Address 46 H Reset value bit7
PHOLD_EX
bit6 00
bit5
bit4
KICKEN
bit3
AUDRST_EN
bit2
MPVCO
bit1
MPEQ
bit0
-
DLY_SEL[1:0]
0
0
0
0
0
-
Bit7 - PHOLD_EX : This bit decides whether the PHOLD signal should be input as DASP in the Servo Block or into P30. 0 : Servo Part's PHOLD signal input as DASP's PHOLD signal (Normal operation). 1 : Pin 30's input used as DASP Part's PHOLD signal (TEST Mode). Bit6 to 5 - DLY_SEL[1:0] : This bit decides the delay time after the HDDLYCTL(44h) Register's Falling Edge by designating the Delay Counter's standard Counter Clock. DLY_SEL[1:0] 00 01 10 11 Clock Frequency 33.8688 MHz 16.9344 MHz 8.4672 MHz 4.2336 MHz Standard Delay Time (Td) 1.86 us 3.72 us 7.43 us 14.86 us
Bit4 - KICKEN :This bit decides whether or not to use the Servo's Kick signal as the DASP's Jitter Controller control bit. 0 : Do not use Servo Part's KICK signal as DASP's Jitter control signal. 1 : Use the Servo Part's KICK signal as DASP's Jitter control signal for internal SRAM CLEAR. Bit3 - AUDRST_EN : This bit decides whether or not to use the AUDRST(48h.0) input from MICOM in Audio Buffering Mode after Jump as the Memory Controller's jitter control signal. 0 : Do not use AUDRST Bit as DASP's Jitter control signal. 1 : Use AUDRST Bit as DASP's Jitter control signal. Bit2 - MPVCO : This bit decides whether or not to use (Phold section + VHD_DLY[3:0]) within the Jitter Control conditions during Phold. 0 : Do not use ( Phold section + VHD_DLY[3:0]) Time as a jitter control condition. 1 : Use ( Phold section + VHD_DLY[3:0]) Time as a jitter control condition. Bit1 - MPEQ : This bit decides whether or not to use (Phold section + Time to PLL LOCK generation) + VHD_DLY[3:0])(= PHOLD_EQ) as a jitter control condition during Phold. 0 : Do not use PHOLD_EQ Time as a jitter control condition 1 : Use PHOLD_EQ Time as a jitter control condition. O When you use the signal above as the jitter control signal, the ECC SRAM's memory Pointer is initialized, and the data is damaged.
94
DATA SHEET
S5L9250B
MISC : Miscellaneous Register Address 47 H Reset value bit7 bit6 EMSEL 0 bit5 0 bit4 bit3 0 bit2 0 bit1 1 bit0 CLK_SV 0
EQ_SPD[3:0]
Bit6 - EMSEL : This bit selects the U bit during DAO output. 1 : Use the P78 input as the DAO Block's Emphasis Bit. 0 : Use the DACCTRL.DEEM(66h.0) Bit input from MICOM as the DAO Block's Emphasis Bit. Bit4 to 0 - EQ_SPD[3:0] : This bit is for selecting the speed of the RF EQ control voltage generator. SPD3 0 0 0 0 0 0 0 0 1 1 1 1 1 SPD2 0 0 0 0 1 1 1 1 0 0 0 0 1 SPD1 0 0 1 1 0 0 1 1 0 0 1 1 0 SPD0 0 1 0 1 0 1 0 1 0 1 0 1 0 Speed 1X 4X 8X 16X 20X 24X 28X 32X 36X 40X 48X 54X 60X Control Mode CLV CLV CLV, CAV MAX 12X CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX Notes
Bit0 - CLK_SV : This bit selects the Servo Part's System Clock. 1 : Use 33.8688 MHz as the Servo Part's System Clock. 0 : Use 40 MHz, the frequency generated using the Servo Part's built-in PLL, as the Servo Part's System Clock.
95
S5L9250B
DATA SHEET
AUDCTL : AUDIO Buffering Control Register Address 48 H Reset value bit7
DEEM_EN
bit6
SCSELP
bit5
SCSEL
bit4
PLCK_WINS
bit3
SUBDENSEL
bit2
SYNCSEL
bit1
-
bit0
AUDRST
0
0
0
0
1
1
-
0
Bit7 - DEEM_EN : 1-Bit DAC De-Emphasis feature's MASK Bit (66h.DEEM & DEEM_EN). 1 : De-Emphasis Masking ON. 0 : De-Emphasis Masking OFF.
Bit6 - SCSELP : This bit decides whether to use scand or scor as the subcode sync output to the CDROM decoder. 0 : scor. 1 : scand. Bit5 - SCSEL : This bit decides whether to use scand or scor in the subcode data handling block as the subcode sync signal after the subcode sync det/prot/ins. 0 : scor. 1 : scand. Bit4 - PLCK_WINS : This bit compares the phase of the detected subcode sync and subcode enable signal to detect the presence of subcode sync. 0 : Do not compare phase. 1 : Compare phase. Bit3 - SUBDENSEL : Subcode sync. pattern detection enable.(When Subcode sync. Insertion, protection mode) Default value is 'H'. Bit2 - SYNCSEL : This bit decides whether to execute subcode sync protection / insertion. 0 : Do not execute subcode sync prot / ins. 1 : Execute subcode sync prot / ins.
Bit0 - AUDRST : MICOM sets this bit to "H" at the end of a jump when one is being executed in Audio Buffering Mode. It is used in the Memory Controller's jitter control to clear the jitter between the Write and Read parts, minimizing the jitter between the Subcode Part and Main Data in Audio Buffering Mode. MICOM must write "L" before carrying out the following action. 1 : Clear the jitter of the Memory Controller. 0 : Do not use in the Memory Controller's jitter control. This bit must be used with the JITCTL.AUDRST_EN(46h.3) bit set to "H".
96
DATA SHEET
S5L9250B
49h Reset value
bit7 0
bit6 C1FLG 0
bit5 C2FLG 0
bit4 -
bit3 -
bit2 -
bit1 OFC2 1
bit0 C2ECC 1
ECCCTRL0 ERAMOD
Bit7 : ERAMOD : C2 Max Erasure correction mode 0 : Carry out Erasure correction when "Number of Erasure = 4". 1 : Carry out Error Correction when "Number of Erasure = 4". Bit6 : C1FLG : Flag generating conditions during C1 correction. 0 : Generate flag even during MAX correction. 1 : Generate flag only when correction is impossible. Bit5 : C2FLG : Flag generating conditions during C2 correction. 0 : Generate flag even during MAX correction. 1 : Generate flag only when correction is impossible. Bit1 : OFC2 : C2 correction mode during overflow. 1 : Correct Error. 0 : Do not correct Error. Bit0 : C2ECC : C2 correction mode selection (when overflowc2 is 1). 0 : Execute 2 Error correction when an overflag is generated during C2 correction. 1 : Execute 1 Error correction when an overflag is generated during C2 correction. (When 2 errors are generated, do not carry out correction, but handle it as impossible to correct.)
97
S5L9250B
DATA SHEET
4Ah ECCCTRL1 Reset value
bit7
JUMPEN
bit6
MRESYNEN
bit5
JITTEREN
bit4
C2PSEL
bit3
C2FGTYPE3
bit2
C2FGTYPE2
bit1
C2FGTYPE1
bit0
C2FGTYPE0
0
0
0
0
1
1
1
1
Bit7 : JUMPEN : 0 : Do not use Servo Part's JUMP signal in ECC PART's C2 correction. 1 : Use Servo Part's JUMP signal in ECC PART's C2 correction. This bit prevents the incorrect correction within CD-DA Mode's Jump or Defect situations. Bit6 : MRESYNEN : 0 : Do not execute syndrome recalculation during max erasure correction. 1 : Execute syndrome recalculation during max erasure correction. Bit5 : JITTEREN : Noise prevention signal when jitter is generated. 0 : When there is jitter, carry out Interpolation according to the ECC results, then output data. 1 : When there is jitter, hold the Interpolation Part's data for 108 Frames before output. Bit4 : C2PSEL : 0 : Separately C2PO's High byte and Low Byte for final data output in CD-ROM Mode. 1 : Do not separate C2PO's High byte and Low byte flag for final data output in CD-ROM Mode, but carry out ORRING before output. Bit3 to 0 : C2FGTYPE[3:0] : C1 Flag Copy Conditions during C2 correction. [3] : C1 Flag Copy conditions for Max Erasure correction. [2] : Flag C1 Copy conditions for Max correction. [1] : Flag C1 Copy conditions during Overflow. [0] : Flag C1 Copy conditions when correction is impossible. 1 : C1 Flag Copy 0 : C2 Flag Generation
98
DATA SHEET
S5L9250B
4Bh
MIXAMPCTL
bit7 DSHD 0
bit6 EQHD 0
bit5 SLON 1
bit4 -
bit3 -
bit2 -
bit1 -
bit0 -
Reset value
Bit7 - DSHD : SLICER HOLD signal selection 0 : HOLD OFF 1 : HOLD ON Bit6 - EQHD : EQ CONTROL HOLD signal selection 0 : HOLD OFF 1 : HOLD ON Bit5 - SLON : Output control for EFMI NOISE elimination (EFMSL is masked in the Slicer Block). 0: Do not output EFMSL. 1: Output EFMSL(Initial value). O EQ_HOLD = ((ATSC+KICK+DFCT) + EHD_DLY[3:0])(=PHOLD_EQ) & EQHD) O DS_HOLD = (DSHD & (ATSC+KICK+DFCT)) O EFMSL_PAD = (SLON & EFMSL)
99
S5L9250B
DATA SHEET
4Ch SBSY Reset value
bit7
SS0WSEL
bit6
SS1WSEL
bit5
SS0WNDRST
bit4
SS1WNDRST
bit3 0
bit2 0
bit1 0
bit0 0
SS0ISEL[1:0]
SS1ISEL[1:0]
0
0
0
0
Bit7 - SS0WSEL : This bit sets the subcode sync(s0) detection window range. 0 : 1 frame 1 : 2 frames
Bit6 - SS1WSEL : This bit sets the subcode sync(s1) detection window range. 0 : 1 frame 1 : 2 frames Bit5 - SS0WNDRST : This bit opens the subcode sync(s0)'s protection window so that the detected sync can be read as subcode sync. 0 : Do not open. 1 : Open. Bit4 - SS1WNDRST : This bit opens the subcode sync(s1)'s protection window so that the detected sync can be read as subcode sync. 0 : Do not open. 1 : Open. Bit3 to 2 SS0ISEL[1:0] : Number of subcode sync(ds0) insertion blocks. 00 : 1 block 01 : 2 blocks 10 : 3 blocks 11 : 4 blocks
Bit1 to 0 SS1ISEL[1:0] : Number of subcode sync(ds1) insertion blocks. 00 : 1 block 01 : 2 blocks 10 : 3 blocks 11 : 4 blocks 4Dh DAOSUB Reset value bit7 bit6 bit5 bit4 00 bit3 bit2 bit1 bit0
M2DSUBCODE[7:0]
Bit7 to 0 - M2DSUBCODE : MICOM inputs subcode into this bit for DIGITAL AUDIO OUT output. The Default is "00", and usually ties the DAO Format's U Bit to "L" for output.
100
DATA SHEET
S5L9250B
51h PLLCTRL0 Reset value
bit7 -
bit6 11
bit5
bit4 -
bit3 -
bit2 -
bit1 0
bit0 0
PLCKSET[1:0]
UPDN[1:0
Bit7 to 5 - PLOCKSET[1:0] : This block selects the Frequency Detector Hold range after the PLL Lock falls. 00 : 4 Frames 01 : 6 Frames 10 : 8 Frames 11 : 10 Frames Bit1 UPDN[1:0] : UP/DOWN current measurement selection (TEST MODE) 00 : Hi-Z for VCO Measurment 01 : Up for UP current measurement 10 : Down for DN current measurement 11 : Reserved
101
S5L9250B
DATA SHEET
52h PLLCTRL1 Initial Value
bit7 TMX1 0
bit6 TMX0 1
bit5 -
bit4 SLPD1 1
bit3 SLPD0 1
bit2 -
bit1 TALGC 0
bit0 -
Bit7 to 6 - TMX[1:0] : TMAX Detection period selection in the Frequency Detector; Selected according to the number of EFM Transitions. TMX1 0 0 1 1 TMX0 0 1 0 1 Content 32 Transitions 64 Transitions 128 Transitions 256 Transitions Recommended Test Notes
Bit4 to 3 - SLPD[1:0] : PD (Phase Detector) selection "00" : UP/DN Phase Detector outputs every EFM/2 edges "01" : Increases UP/DN width to 1 PLCK at "00". "10" : UP/DN Phase Detector outputs every EFM edges "11" : Increases UP/DN width to 1 PLCK at "10". Bit1 - TALGC : CLV/CAV selection signal. 0 : CLV (recommended for all modes) 1 : CAV
102
DATA SHEET
S5L9250B
53h PLLCTRL2 Initial Value
B7 iDACp5 1
B6 iDACp4 0
B5 iDACp3 0
B4 iDACp2 0
B3 iDACp1 0
B2 iDACp0 0
B1 VCOFIX 0
B0 VCOHD 0
Bit7 to 2 - iDACp [5:0]:Charge Pump UP current gain adjustment (Only applicable to PD. Selected by speed). Charge Pump UP current = N * Iref Here, N is the decimal value shown by iDACp [5:0], and Iref = 95A (RDAC = 22k) Bit1 - VCOFIX : Prevents PLL errors during DISC STOP. 0 1 Normal VCO Operation Fix VCO voltage to 1.65 V
Bit0 - VCOHD : VCO Defect Hold selection (PHOLD_VCO & VCOHD). 0 : Hold OFF 1 : Hold ON 54h PLLCTRL3 Initial Value B7 iDACn5 1 B6 iDACn4 0 B5 iDACn3 0 B4 iDACn2 0 B3 iDACn1 0 B2 iDACn0 0 B1 B0 SLEFM 0
Bit7 to 2 : iDACn[5:0] : Charge Pump Down current gain adjustment (Only applicable to PD. Selected by speed). Charge Pump Down current = N * Iref Here, N is the decimal value shown by iDACn[5:0], and Iref = 95A (RDAC = 22k) Bit1 to 0 - SLEFM : Extracts PLL PD input signal and Channel Clock, and chooses the signal that latches the Channel Data. 1 : TEST EFMSL signal input (P95). 0 : Slicer's EFMSL input.
103
S5L9250B
DATA SHEET
55h PLLCTRL4 Initial Value
B7 0
B6 1
B5 0
B4 0
B3 0
B2 0
B1 0
B0 0
FDGAIN[7:0]
Bit7 to 0 - FDGAIN[7:0] : The minimum pulse width data of the current output to the FDO by the Charge Pump. The minimum pulse width, Tlsb, is found by the following formula: Tlsb = 2 *( NFDGAIN+1)/fsys Here, fsys ; System (33.8688 MHz) NFDGAIN ; Decimal Value shown by FDGAIN[7:0].
Tmax Error
Ne[n-1]
Ne[n] Tmax TFDGAIN
Ne[n+1]
Charge Pump Current
Icp
Tmax Detection Period TFDGAIN = Ne[n] * Tlsb Ne[n] o (1, 10)
56h PLLCTRL5 Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
PWM[7:0]
Bit7 to 0 - PWM[7:0] : Same timing generated as 55h for ALGC PWM use. 57h SLICTRL0 Initial Value B7 0 0 0 B6 B5 B4 B3 SLFIX[6:0] 0 0 0 0 B2 B1 B0
Bit6 to 0 : - SLFIX[6:0] : Slicer level fix voltage (25.7 mV/ LSB, VDD = 3.3 V). 0 1 1 _ 1 1 1 1 : VDD // 0 0 0 _0 0 0 0 0 : Vref ( 1.65 V ) // 1 0 0 _0 0 00 0 : GND
104
DATA SHEET
S5L9250B
58h SLICTRL1 Reset value
B7 LPFS 0
B6 RES2 0
B5 RES1 0
B4 RES0 0
B3 SLEN 0
B2 INLG2 0
B1 INLG1 0
B0 INLG0 0
Bit7 - LPFS: 1 : LPF1 Select For CD 24X, 32X, 40X, 48X. 0 : LPF0 Select For CD 1X, 4X, 8X, 16X. Bit6 to 4 - RES2 to 0 : RFI block Input impedance , Rin. "000": 1.5k "010": 2.5 k "100" : 5k "110" : 10k "001": 2k "011": 3k "101" : 6.5k Bit3 - SLEN : Slice HOLD use. 1 : Use HOLD. 0 : Do not use HOLD. Bit2 to 0 - INLG2 to 0 : Data Slicer AMP Gain Selection 1) AMP Gain ( Ka = 1 + Ra2 / Ra1 , Ra1=10 Kohm) INLG2 0 0 0 0 1 1 1 1 INLG1 0 0 1 1 0 0 1 1 INLG0 0 1 0 1 0 1 0 1 Ka [times] 1.0 1.5 2.0 5.0 10 20 30 50 Ra2 [Kohm] 0 5 10 40 90 190 290 490
"111" : 40k
105
S5L9250B
DATA SHEET
59h SLICTRL2 Reset value
B7 TSLCS 0
B6 EQFIX 0
B5 PKEN -
B4 PKCTL -
B3 0
B2 DFRL[2:0] 0
B1 0
B0 -
Bit7 : TSLCS: 1 : Slicer Level Fix Voltage Monitor 0 : Duty Feedback Data Slicing Level Voltage Monitor Bi6 : EQFIX: 1 : EQ control voltage output by EQVSET[6:0] 0 : Normal Operation Bit5 : PKEN : RFsignal PEAKING prevention after DEFECT. 1 : Apply PEAKING prevention. 0 : Do not apply PEAKING prevention. Bit4 : PKCTL : Use PHOLD signal for SLICE as the SLICER HOLD signal. (Used together with DSHD, and only applicable when SLICTRL1.SLEN (58h.3) is 'H'.) DSHD 0 0 1 1 PKCTL 0 1 0 1 No HOLD signal Use DEFECT signal generated in SLICE Use RF's DEFECT signal Use RF DEFECT + SLICE DEFECT signal Function
Bit3 to 1 : DFRL[2:0] : DEFECT detection signal period for SLICE. 000 : PLCK*28T 001 : 42T 010 : 56T 011 : 70T 100 : 84T 101 : 98T 110 : 112T 111 : 126T
106
DATA SHEET
S5L9250B
5Ah Reset value
bit 7 0
bit 6
SBFLUSHEN
bit 5 -
bit 4 -
bit3 WSEL1 0
bit 2 WSEL0 0
bit 1 GSEL1 0
bit 0 GSEL0 0
EFMCTRL1 SUBCON
0
Bit 7 : SUBCON : Sync protection WINDOW section selection. 1 : Output after synchronizing MAIN DATA and SUBCODE. 0 : Output without regard to MAIN DATA and SUBCODE sync. Bit 6 : SBFLUSHEN : SUBCODE Buffer Flush MASK Bit. 1 : Flush SUBCODE Buffer when Jitter is generated. 0 : Prohibit SUBCODE Buffer Flush when Jitter is generated. Bit 5 - SSEL ; SPINDLE PWM output Source selection signal. (Test bit) 1 : Pre D-EQ signal output. 0 : Post D-EQ signal output. Bit 3 to 2 : WSEL[1:0] : Sync Protection WINDOW Section Selection WSEL1 0 0 1 1 WSEL0 0 1 0 1 Frame Sync Protection Window 3 clocks 7 clocks 13 clocks 20 clocks
Bit 1 to 0 : GSEL[1:0]: Number of frames for Frame Sync insertion. GSEL1 0 0 1 1 GSEL0 0 1 0 1 Number of Frames for Frame Sync Insertion 2 Frames 4 Frames 8 Frames 13 Frames
107
S5L9250B
DATA SHEET
5Bh EFMCTRL2 Reset value
bit 7 -
bit 6
CK33MSEL
bit 5 -
bit 4 -
bit3 -
bit 2 -
bit 1 GFSDET 0
bit 0 WNDRST 0
0
Bit 6 : CK33MSEL : 33.8688 MHz System Clock output selection bit (PAD 40). 1 : 33.8688 MHz System Clock output Enable. 0 : 33.8688 MHz System Clock output Disable. Bit 1 : GFSDET : Good Frame Sync detection condition. 1 : Accept as GFS even if there is a 1-bit difference with detected Sync. 0 : Perfect synchronization between detected and inserted Sync. Bit 0 : WNDRST : Window Reset. Open window if this bit is "High". It is used when you want to lock the window quickly by detecting new sync during track jump. 5Ch MTRCTRL Reset value bit 7 LJUMP 0 bit 6 LOCKEX 0 bit 5 MON_EX 0 bit 4 DCTL 0 bit3 SPD3 0 bit 2 SPD2 0 bit 1 SPD1 0 bit 0 SPD0 1
Bit7 - LJUMP : If MICOM sets this bit to "H" during a Long Jump or 2/3 Stroke, you must write "L" first, then "H" before the next operation. Before setting the LONG JUMP Bit to "H", first write the EQ control voltage applicable to EQVSET[6:0](45h). 0 1 Normal Operation Long Jump
Bit6 - LOCKEX : Chooses and inputs the Servo Part's CLV LOCK signal (for TEST). 0 1 Receive CLV LOCK signal from interior (DASP), and output CLV LOCK signal from PAD 79. Receive CLV LOCK signal from exterior (PAD29), and output CLV LOCK signal from PAD 79.
Bit5 - MON_EX : This bit decides whether the Servo Part should accept the Spindle Motor ON/OFF signal from the exterior, or the DASP output signal. The SMONsignal is output to PAD27. 0 1 Input DASP's SMON signal from the interior to the SERVO. Input the SMON signal to P29 (TEST MODE).
Bit4 - DCTL : Disc Motor Control Mode. 0 1 CLV CAV
108
DATA SHEET
S5L9250B
Bit3 to 0 - SPD[3:0] : Speed Mode. SPD3 SPD2 SPD1 SPD0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Speed 1X 4X 8X 16X 20X 24X 28X 32X 36X 40X 48X 54X 60X 1.5 1.5 1.5 1 1 1 PLL Division Rate 32 8 4 3 3 2 Control MODE CLV CLV CLV, CAV MAX 12X CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX CAV MAX
Incompatible VCO band 3 VCO band 2 VCO band 1
109
S5L9250B
DATA SHEET
5Dh FCSEL Reset value
bit 7 FPLUS 0
bit 6 ULHD 0
bit 5 FAGD 1
bit 4 RCAV 0
bit3 FNCW1 0
bit 2 FNCW0 0
bit 1 FCW1 1
bit 0 FCW0 0
Bit7 - FPLUS : PLUS ONLY MODE. Carries out acceleration control when LOCK is HIGH. Deceleration control prohibited. 1 : Execute 0 : Do not execute Bit6 - ULHD : Maintain previous value when CLV is unlocked. 1 : Use previous value 0 : Do not use previous value Bit5 - FAGD : FREQUENCY CONTROL AUTO GAIN DOWN 1 : -12dB GAIN DOWN when unlocked. 0 : No Gain Down even when unlocked. Bit4 - RCAV : ROUGH CAV MODE. 1 : When unlocked, limit the number of Disc Motor rotation to between the MIN and MAX. If a Lock Flag is generated, revert to CLV Mode. . 0 : AFC output when unlocked. Bit3 to 2 - FNCW1 to 0 : AFC UNCONTROL RANGE ( Dead Zone ) SETTING. FNCW1 0 0 1 1 FNCW0 0 1 0 1 Content Do not use uncontrolled area. Uncontrolled area 6.25% Uncontrolled area 12.5% Uncontrolled area 25%
Bit1 to 0 - FCW1 to 0 : AFC LINEAR CONTROL RANGE SETTING. FCW1 0 0 1 1 FCW0 0 1 0 1 Initial Value 200H 480H 5C0H RESERVED Division Rate (N) 1 2 4 Linear Control Range 10% 20% 40%
110
DATA SHEET
S5L9250B
5Eh PCSEL Reset value
bit 7 00
bit 6
bit 5 FGWDT 0
bit 4 MOTSEL 0
bit3 PCEN 1
bit 2 PCR 0
bit 1 PCW1 1
bit 0 PCW0 1
FGSEL[1:0]
Bit7 to 6 - FGSEL[1:0] : This bit selects the FG Counter to react to the 6/12 pole MOTOR's various FG. FGSEL[1:0] 00 01 10 Division Rate 1 2 3
11 6 Bit5 - FGWDT ; FG signal ONESHOT PULSE WIDTH (Standard signal is generated at each disc rotation). 1 : 75 us width. 0 : 150 us width. Bit4 - MOTSEL ; SPINDLE MOTOR selection signal. 1 : 12 pole Motor. 0 : 6 pole Motor. Bit3 - PCEN ; PHASE CONTROL ENABLE 1 : Enable Bit2 - PCR : PHASE CONTROL RANGE 1 : Execute within AFC 25%. 0 : Execute within AFC 50%. Bit1 to 0 - PCW1 to 0 : Phase Control period selection. PCW1 0 0 1 1 PCW0 0 1 0 1 Control Period 24 Frames 48 Frames 96 Frames 192 Frames 0 : Disable
5Fh PCOFFS Reset value
bit 7 POFFS7 0
bit 6 POFFS6 0
bit 5 POFFS5 0
bit 4 POFFS4 0
bit3 POFFS3 0
bit 2 POFFS2 0
bit 1 POFFS1 0
bit 0 POFFS0 0
Bit7 to 0 : POFFS7 to 0 : Adds a set Offset value to the final output value according to motor type, in order to minimize the direct current residual deviation.
111
S5L9250B
DATA SHEET
60h EMOSEL Reset value
bit 7 CLVHD 0
bit 6 SMON1 0
bit 5 SMON0 0
bit 4 SPOLAR 0
bit3 KICK 0
bit 2 BRAKE 0
bit 1 PWMCA1 1
bit 0 PWMCA0 0
Bit7 : CLVHD : Mask signal that holds the Spindle Motor Control if a disc defect or an external shock is detected in the set during Seek in the Servo IC. "L" : Do not hold Spindle Motor control (Normal operation). "H" : Hold Spindle Motor control. Bit6 to 5 : SMON1 to 0 : Disc Motor On Mode SMON1 0 1 1 SMON0 0 1 Operation Disc Motor OFF , Fix ERROR handling OP AMP output to VDD/2 Disc Motor ON , Fix SMOF / SMOP output to Hi-Z Disc Motor ON , Normal control operation
Bit4 : SPOLAR : Disc Motor Rotation Direction. 0 : Clockwise Direction. 1 : Counter clockwise Direction. Bit3 : KICK : Disc Motor MAX Acceleration. 0 : Normal Control operation. 1 : Fix SMOF / SMOP output to VDD. Bit2 : BRAKE : Disc Motor MAX deceleration. 0 : Normal Control operation. 1 : Fix SMOF / SMOP output to GND. Bit1 to 0 : PWMCA1 to 0 : PWM Carrier Frequency Selection. PWMCA1 0 0 1 1 PWMCA0 0 1 0 1 PWM Carrier Frequency 7.35 * 2 kHz 7.35 * 4 kHz 7.35 * 12 kHz 7.35 * 36 kHz
112
DATA SHEET
S5L9250B
61h, 62h CAVSEL1 Reset value CAVSEL2 Reset value
bit 7 0 0
bit 6 CAVCK[2:0] 0 0
bit 5 0 0
bit 4 -
bit3 -
bit 2 0
bit 1 0 0
bit 0 0 0
CAVR[9:8]
CAVR[7:0] 0 0
In CAV Mode, Disc rotation velocity can be found using the following formula: DISC RPM = (fsys * Nck * 10) / (1024 * ( 1793 - Ncavr )) Here, fsys ; System Clock (33.8688 MHz) Ncavr ; Decimal Value shown by CAVR[9:0] Ncavr = CAVR[i] * 2i ( 1 CAVR 381H) Nck ; Clock division value selected by CAVCK[2:0] CAVCK[2] 0 0 0 0 1 1 1 CAVCK[1] 0 0 1 1 0 0 1 CAVCK[0] 0 1 0 1 0 1 0 Nck 1 2 4 8 16 32 64 Disc RPM Range (MIN RPM at CAVR==1, MAX RPM at 381H) 184.6 to 369.1 369.1 to 738.3 738.3 to 1476.6 1476.6 to 2953.1 2953.1 to 5906.3 5906.3 to 11812.5 11812.5 to 23625.0
MICOM Selection Method. (1) Select the number of rotations that you want. (2) Select Nck value according to the number of rotations. <- CAVCK[2:0] selection (3) Calculate initial value Ncavr using the formula given above ( Binary ). (4) CAVCK[2:0], CAVR[9:0] Data transmission. The AFC/APC control range can change according to the Ncavr variance. ; AFC control range increase (7.14 - 14.28%). APC control range decrease (100 - 50%).
113
S5L9250B
DATA SHEET
63h DAOCTRL Reset value
bit 7 DAOEN 0
bit 6 -
bit 5 -
bit 4 -
bit3 MEMPHIN 1
bit 2 copyen 0
bit 1 emphen 0
bit 0 acmode 0
Bit 7 - DAOEN : DIGITAL AUDIO OUT Enable/Disable Bit. 1 : Output DIGITAL AUDIO OUT from S5L9250B. 0 : Do not output DIGITAL AUDIO OUT from S5L9250B. Bit 3 - MEMPHIN : DIGITAL AUDIO OUT Block's CONTROL signal input Bit. 1 : Use EMPH signal as the DAO Block input in P78. 0 : Use DEEM(66h.0) & DEEM_EN(48h.7) signal as DAO BLOCK input. Bit 2 to 0 decides whether to allow COPY during DAO output, execute pre-emphasis, and to have 2 or 4 audio channels. Its value is decided by MICOM. Bit 2 - COPYEN : This bit decides whether to allow Digital Audio Out Block Copy. 1 : Allow Digital Copy. 0 : Prohibit Digital Copy. Bit 1 - EMPHEN : This bit tells you if there is pre-emphasis on the Digital Audio Out block's output. 1 : Pre-Emphasis ON 0 : Pre-Emphasis OFF. Bit 0 - ACMODE : This bit tells you if the DAO output Audio is 2-Channel or 4-Channel. 1 : 4-Channel Audio 0 : 2-Channel Audio.
114
DATA SHEET
S5L9250B
64h CAVCTRL Reset value
bit 7 ROTSEL 0
bit 6 ROVS2 0
bit 5 ROVS1 1
bit 4 ROVS0 1
bit3 RIS1 1
bit 2 RIS0 1
bit 1 FAL1 0
bit 0 FAL0 1
Bit7 : ROTSEL : Motor Rotation Direction Polarity Switching (Initial Value = 0) 0 : Direction when the DIRROT signal input from the Drive IC is "H". 1 : Direction when the DIRROT signal input from the Drive IC is "L". Bit6 to 4 : ROVS2 to 0 : Motor runaway discrimination standard selection ROVS2 0 0 0 0 1 1 1 1 ROVS1 0 0 1 1 0 0 1 1 ROVS0 0 1 0 1 0 1 0 1 Content Above 3000 RPM Above 4000 RPM Above 5000 RPM Above 6000 RPM Above 7000 RPM Above 8000 RPM Above 10000 RPM Above 12000 RPM
Bit3 to 2 : RIS1 to 0 : Delay adjustment after GFS is "H" and before CLV LOCK becomes "H" (Initial Value = '11'). 00 : CLV LOCK is "H" when GFS's "H" continues for more than 2 WFCK (or FRAME SYNC). 01 : CLV LOCK is "H" when GFS's "H" continues for more than 4 WFCK (or FRAME SYNC). 10 : CLV LOCK is "H" when GFS's "H" continues for more than 8 WFCK (or FRAME SYNC). 11 : CLV LOCK is "H" when GFS's "H" continues for more than 16 WFCK (or FRAME SYNC). Bit1 to 0 : FAL1 to 0 : Delay adjustment after GFS is "L" and before CLV LOCK becomes "L" (Initial Value = '01'). 00 : CLV LOCK is "L" when GFS's "L" continues for more than 256 WFCK (or FRAME SYNC). 01 : CLV LOCK is "L" when GFS's "L" continues for more than 128 WFCK (or FRAME SYNC). 10 : CLV LOCK is "L" when GFS's "L" continues for more than 64 WFCK (or FRAME SYNC). 11 : CLV LOCK is "L" when GFS's "L" continues for more than 32 WFCK (or FRAME SYNC).
115
S5L9250B
DATA SHEET
66h DACCTRL Reset value
bit 7 DN 0
bit 6
bit 5
bit 4 H2L3 0
bit3 -
bit 2 MUTEL 0
bit 1 PDL 1
bit 0 DEEM 0
SDACCK PWRSAV E 0 0
Bit7 : DN : 1-bit DAC speed mode. 0 : Normal speed. 1 : Double speed. Bit6 : Built-in 1-Bit DAC System Clock Source selection signal. 0 : Input 17MHz system clock to 1-bit DAT within the IC. 1 : Input system clock output from an external IC supplying CD-AUDIO DATA to 1-Bit DAC. Bit5 : PWRSAVE : POWER SAVE mode. 0 : Normal Operation. 1 : Power Saving Mode ON. Bit4 : H2L3 : Built-in 1-Bit DAC System clock division rate => 16.9344MHz. 0 : Divide PAD 95 input CLOCK by 3 for use (50.8MHz / 3). 1 : Divide PAD 95 input CLOCK by 3 for use (33.8MHz / 2). Bit2: MUTEL : 1-Bit DAC Mute Control Bit (Initial state is ON). 0 : 1-Bit DAC Mute ON. 1 : 1-Bit DAC Mute OFF (Normal Operation). Bit1: PDL : 1-Bit DAC POWER SAVING Control Bit. 0 : 1-Bit DAC Power Saving Mode ON. 1 : 1-Bit DAC Power Saving Mode Off (Normal Operation). Bit0 : DEEM : De-Emphasis Enable (48h.7 DEEM_EN Bit and AND Operation). 0 : De-Emphasis OFF 1 : De-Emphasis ON
116
DATA SHEET
S5L9250B
67h DATTN Reset value
bit 7 -
bit 6 -
bit 5 ATTL5 0
bit 4 ATTL4 0
bit3 ATTL3 0
bit 2 ATTL2 0
bit 1 ATTL1 0
bit 0 ATTL0 0
Bit5 to 0 : ATTL5 - ATTL0 : Digital Attenuation Level (both L/R). Controls 1-Bit DAC output. ATTL5 to ATTL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Attenuation Level (dB) 0 -0.28 -0.42 -0.56 -0.71 -0.86 -1.01 -1.16 -1.32 -1.48 -1.64 -1.80 -1.97 -2.14 -2.32 -2.50 -2.68 -2.87 -3.06 -3.25 -3.45 -3.66 -3.87 -4.08 -4.30 -4.53 -4.76 -5.00 -5.24 -5.49 -5.75 -6.02 ATTL5 to ATTL0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Attenuation Level (dB) -6.30 -6.58 -6.88 -7.18 -7.50 -7.82 -8.16 -8.52 -8.89 -9.28 -9.68 -10.10 -10.55 -11.02 -11.51 -12.04 -12.60 -13.20 -13.84 -14.54 -15.30 -16.12 -17.04 -18.06 -19.22 -20.56 -22.14 -24.08 -26.58 -30.10 -36.12 -A
117
S5L9250B
DATA SHEET
2) Read Register 70h INTSTAT Reset value bit 7 SUQINT 0 bit 6 REVINT 0 bit 5 ROVINT 0 bit 4 JITINT 0 bit3 bit 2 bit 1 bit 0 -
Bit7 : SUQINT : Subcode Q Sync Interrupt. Bit6 : REVINT : When Disc is in reverse rotation, an Interrupt is generated at each disc rotation (FG/6). Bit5 : ROVINT : If the MOTOR's rotation velocity exceeds that set by MICOM (ROVS[2:0]), an Interrupt is generated at each disc rotation (FG/6). Bit4 : JITINT : "H" when there is jitter in the DASP PART's MEMORY Controller. FRAME Counter Value Read Register Address 71h 72h bit 7 FC15 FC7 bit 6 FC14 FC6 bit 5 FC13 FC5 bit 4 FC12 FC4 bit3 FC11 FC3 bit 2 FC10 FC2 bit 1 FC9 FC1 bit 0 FC8 FC0
Bit15 to 0 : FC[15:0] Carries out UP-COUNT for each frame and notifies MICOM. If actual data is written on a different linear speed because of differences in the disc manufacturing process, this bit is used for correcting the linear speed difference by allowing MICOM to calculate it.
SUBQ DATA Read Register Address 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch bit 7 CTL3 TNO7 INDEX7 MIN7 SEC7 FRM7 ZERO AMIN7 ASEC7 AFRM7 bit 6 CTL2 TNO6 INDEX6 MIN6 SEC6 FRM6 ZERO AMIN6 ASEC6 AFRM6 bit 5 CTL1 TNO5 INDEX5 MIN5 SEC5 FRM5 ZERO AMIN5 ASEC5 AFRM5 bit 4 CTL0 TNO4 INDEX4 MIN4 SEC4 FRM4 ZERO AMIN4 ASEC4 AFRM4 bit3 ADR3 TNO3 INDEX3 MIN3 SEC3 FRM3 ZERO AMIN3 ASEC3 AFRM3 bit 2 ADR2 TNO2 INDEX2 MIN2 SEC2 FRM2 ZERO AMIN2 ASEC2 AFRM2 bit 1 ADR1 TNO1 INDEX1 MIN1 SEC1 FRM1 ZERO AMIN1 ASEC1 AFRM1 bit 0 ADR0 TNO0 INDEX0 MIN0 SEC0 FRM0 ZERO AMIN0 ASEC0 AFRM0
118
DATA SHEET
S5L9250B
2) Read Register 7Dh C1EBYTE Reset value 0 0 0 bit 7 bit 6 bit 5 bit 4 0 bit3 0 bit 2 0 bit 1 0 bit 0 0
C1EBYTE[8:1]
C1EBYTE[8:0] : Number of Error bytes generated during C1 correction calculated according to SUBCODE Sync.
7Eh C1ECODE Reset value
bit 7 0
bit 6 0
bit 5 0
bit 4 0
bit3 0
bit 2 0
bit 1 0
bit 0 0
C1EBYTE[0], C1ECODE[6:0]
C1ECODE[6:0] : Number of uncorrectable error codewords generated during C1 correction. Updated at each SUBCODE Sync.
7Fh DPSTAT Reset value
bit 7 SBQERR 0
bit 6 -
bit 5 -
bit 4 -
bit3 -
bit 2 -
bit 1 -
bit 0 -
Bit7 : SBQERR : Shows the presence of errors in SUBCODE 80byte at each SUQINT. 1 : Errors present after SUB-Q CRC Check. 0 : No errors present after SUB-Q CRC Check. 80h C2EBYTE Reset value 0 0 0 bit 7 bit 6 bit 5 bit 4 0 bit3 0 bit 2 0 bit 1 0 bit 0 0
C2EBYTE[8:1]
C2EBYTE[8:0] : The Number of Error bytes generated during C2 correction calculated according to the SUBCODE Sync.
119
S5L9250B
DATA SHEET
81h C2ECODE Reset value
bit 7 0
bit 6 0
bit 5 0
bit 4 0
bit3 0
bit 2 0
bit 1 0
bit 0 0
C2EBYTE[0], C2ECODE[6:0]
C2ECODE[6:0] : The number of uncorrectable error codewords during C2 correction calculated according to SUBCODE Sync. 82h RBCH Reset value 83h RBCL Reset value 0 0 0 0 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 0 bit3 0 0 bit 2 0 bit 5 bit 4 bit3 bit 2 bit 1 0 bit 1 0 bit 0 0 bit 0 0
RBC[11:8]
RBC[7:0]
RBC[11:0] : Read Frame Counter value during JITTER Interrupt generation.
84h WBCH Reset value 85h WBCL Reset value
bit 7
bit 6 -
bit 5
bit 4
bit3 0
bit 2 0 bit 2 0
bit 1 0 bit 1 0
bit 0 0 bit 0 0
WBC[11:8]
bit 7 0
bit 6 0
bit 5 0
bit 4 0
bit3 0
WBC[7:0]
WBC[11:0] : Write Frame Counter value during JITTER Interrupt generation.
120
DATA SHEET
S5L9250B
CLOCK GENERATION The CLKEGN block generates all the clocks used within the CD-DSP part and the signals related to the reset of each block. All clocks used in the CD-DSP are made from the 33.8688 MHz frequency generated from a crystal. These clocks go through muxing according to the speed and audio output format mode operation demanded by MICOM, and are then output. During scan test, all clocks operate at the clock speed input into the sysclk (33.8688 MHz function operation). 1) I/O Description Pin Name i_rstb sysclk wfck dctl spd_mode out_mode i_test_en o_rstb rfck o_RFCntENb o_WFCntEnb
o_JitterCntEnb
I/O I I I I I I I O O O O O O O
To/From External External EFM MICOM MICOM MICOM External Internal Block Clock Gen Clock Gen Clock Gen Clock Gen Clock Gen Clock Gen 33.8688MHz clock
Descriptions System Reset From Outside 7.35kHz clock from EFM Disc mode signal from MICOM Playing speed mode Audio output mode (0: 24-bit mode, 1:32-bit mode) Scan test enable (1: test mode) reset signal to each block. Negative logic 7.35kHz clock at x'tal Read frame counter enable. Write frame counter enable. Jitter counter enable. ECU block reset signal. Low active. Interpolator Data address request signal reset. High active
o_rstECUb o_ReqAddrRst
121
S5L9250B
DATA SHEET
CHANNEL CLOCK RECOVERY PLL Features Single LPF (Loop Filter) regardless of speed 50% wide capture range Loop gain automatic adjustment feature for CAV control Disc Defect and Shock handling Servo track jump handling Sync. frame noise reduction Programmable charge pump current setting (two 6-bit iDAC) Block Diagram
AVDD SYSTEM CLOCK RDAC Multiplexer INPUTS S1 S4 EFMSL EFMNR TEST_EFM (fr. Slicer) C1 C2 ENB D TMAX Detector Charge Pump Control (PWM Gen.) FDUP
FDDN PWH LSB width select TMAX Detection Period select Charge Pump Gain Select PDUP PUMPO
INPUT SELECT PLLHD
Charge Pump
Hogge Phase Detector DECISION CIRCUIT 1/2 1/N Voltage Controlled Oscillator
PDDN VCTRL VALC ALCLF
RVCO MICOM SPEED & MODE Demodulation Block AVSS
RVCO32 ALC Control and RVCO select ALCO
122
DATA SHEET
S5L9250B
Block Description PLL receives a signal called EFMI as its input, which zero crosses the signal input from the RF block into in the slicer, handles it in digital signal level, and outputs it. The PLL synchronizes this standard input signal (EFMI) with its built-in VCO clock frequency and phase. The VCO clock in sync with the EFMI signal is appropriately divided according to speed. Jitter is eliminated by latching the input signal once with this clock. This is to reduce the errors when demodulating back to the original signal in the DSP block. The PLL is often called the decision circuit. I/O Definition Symbol EFMSL EFMNR EFMGN iDACO VCTRL RVCO RDAC VALC ALGCO ALCLF PLLHD CLVLOCK PLCK EFML PLOCK PLOCK1 CK33 Other MICOM Registers MICOM Registers Please refer to the MICOM Register Descriptions. I/O I I I O I B B I O I I I O O O O I I Simple Slicer Output Slicer Output with Noise Rejection EFM Pattern Generation by DSP (for Test) Charge Pump Output VCO Control Voltage VCO V/I Converting Resistor Biasing Resistor for iDAC at Charge Pump Reference Voltage for Automatic Loop Gain Control (ALC) ALGC PWM Output (Digital Level) ALC PWM LPF Output (DC Voltage, Analog Level) Set High when DFCT, SHOCK, Track Jump CLV LOCK indicator VCO Clock Divided by N Retimed EFM by PLCK PLL LOCK indicator with Hysterisis PLL LOCK indicator without Hysterisis SYSTEM CLOCK 33 MHz MICOM Interface From MICOM I/F To Data Slicer From DSP From CLV/CAV To DSP To DSP From DSP Description comment for one-chip From Data Slicer
123
S5L9250B
DATA SHEET
DATA SLICER & EQ REMOVAL Data Slicer Data Slicer Characteristics 2 STEP integration area selection conversion RF input size: min = 0.5 Vpp , Max = 1.5 Vpp 8 STEP RF input Impedance select 8 STEP AMP Gain select Hold feature Noise Rejection circuit
Block Diagram
PLCK DFRL<2:0>
Defect Generating Circuit
PEAK
SLON EFMSL_pad EFMSL (to PLL) Noise Rejection Cin1 RFI1 Rin RES[2:0] Vref
+ PLCK PLLOCK
EFMNR (to PLL) R11
C11
R21
C21 R20 C20
EFMCOMP
R10 C10
COMP Vp OP AMP INLG[2:0]
+ Ra1 -
LPFS Vref LPF0 LPF1
TSLCS Ra2
124
DATA SHEET
S5L9250B
Block Description This block uses the EFM signal's DSV characteristics to integrate the comparator output's duty and track the slicing level to use the Duty Feedback method. The Noise Rejection has a pulse width of less than 1.5T for Data Slicing output. I/O Definition Symbol RFI EFMCOMP EFMSL LPF0 LPF1 LPFS TSLCS DSLCS RES[2:0] INLG[2:0] HOLD EFMNR PLCK PLLOCK PEAK I/O I O O I I I I I I I I O I I O Description Eye Pattern from RF Duty Feedback Slicer output Duty Feedback Slicer, Current control method Slicer output LPF input ( CD X1,X4,X8) LPF input (CD X16, X24) 'L' : LPF0 'H' : LPF1 'H' : Slice Level Fix voltage 'L' : Slicer Level voltage 'L' : Duty Feedback Slicer 'H' : DIGITAL Method Slicer 8Step's input Impedance select Input Gain select Hold signal in case of Defect Slice signal after Noise Rejection Channel Bit Clock PLL Lock signal Defect detection signal Comment for one-chip PAD PAD MONITOR PAD PAD MICOM (Reset : L) MICOM (Reset : L) MICOM (Reset : L) MICOM (Reset : LLL) MICOM (Reset : LLL) Internal (Defect : H) Internal Internal Internal (Lock : H)
125
S5L9250B
DATA SHEET
Related Register SLICTRL1 58H Reset value B7 LPFS 0 B6 RES2 0 B5 RES1 0 B4 RES0 0 B3 SLEN 0 B2 INLG2 0 B1 INLG1 0 B0 INLG0 0
SLICTRL2 59H Reset value
B7 TSLCS 0
B6 EQFIX 0
B5 PKEN 0
B4 PKCTL 0
B3 DFRL2 0
B2 DFRL1 0
B1 DFRL0 0
B0 -
Timing Diagram * * After the NR input signal transition is generated, the block operates only for reverse transitions larger than the Noise Rejection width. The block operates only when PLL is in Lock state.
PLCK Tnr Noise Reject Input Noise Reject Output Tnr Tnr Tnr
Noise Rejection width: Tnr = 1.5 * Tch Time to the second Rising Edge from the point after input signal Transition (in Lock status, sync with PLCK's Falling Edge).
126
DATA SHEET
S5L9250B
Control Characteristics Bit Clock Frequency-voltage conversion output for Analog Equalizer control; Center frequency selection change and output fix mode Input frequency range: 0.5 * fc to 1.5 * fc ( fc: F/V Center Freq. ) F/V Slope : + 1.65 / fc [Volt/Hz] ( fc's 10% change 0.165V output change ) Linearity: < 7% ( Ideal output characteristic standard ) Hold feature Block Diagram
Preset
F_CLK PLCK
7-bit Counter 7 PE: preset Enable
HOLD, EQFIX
Comparative signal Divider I/N SPD[2:0]
DAC sample
EQCTL
CK33
Standard signal Divider I/N
REF
Edge Detect
Block Diagram Description CK33-divided REF signal and the PLCK-divided comparative signal are countered, and that counter value is output to the 7-bit DAC for use in the RF Equalizer's control voltage. In case of a defect, a Hold signal is received to hold to the previous control voltage, and a MICOM Register (EQFIX) controls the control voltage to eqvset[6:0].
127
S5L9250B
DATA SHEET
I/O Definition Symbol PLCK EQFIX HOLD EQCTL CK33 EQ_SPD[3:0] I/O I I I O I I Channel Bit Clock EQ output voltage controlled to Eqvset [6:0] Hold EQ output to previous value in case of Defect EQ output voltage SYSTEM CLOCK SPEED MODE Description comment for one-chip Internal MICOM Register Internal PAD PAD MICOM Register
Related Register and Bit Description ; Please refer to 5.2.5.3.1.5. Timing Diagram
V
3*VDD/4 VDD/2 VDD/4 bit clock freq.
fc/2
fc
1.5fc
Camparative signal (PLCK)
Sample Standard Signal pe signal
Counter Counter Cnt start Sampling Cnt value for dac output
128
DATA SHEET
S5L9250B
EFM DEMODULATION AND SYNC PROTECTION Characteristics * EFM Demodulator Converts NRZI Pattern's input signal to NRZ. Converts 14-Channel Bit 8-data bit. Subcode Sync detection. * Sync Detection/Protection/Insertion. EFM Sync Protection Window Selection. Frame Sync Insertion Frame number selection. Frame Sync Detection/Protection/Insertion. Block Diagram
CDEFM[13:0]
EFM Demodulator
EFMD[7:0]
PLCK NRZI Converter EFMI Related MICOM Control BIT DFRSY SYNC Handling SYMCK WFCK
EFM Demodulator's Block Diagram Block Description The Bitstream read from the Disc goes through waveform remodelling in the RF and Data Slicer, and is input as NRZI Pattern to the EFM block (EFMI). The EFMI signal phase is synchronized with PLCK (1X : 4.3218 MHz, NX : N * 4.3218 MHz), the PLL output signal locked to the Channel Bit frequency, and then converted into NRZ Pattern. Figure 1 shows the NRZI Conversion's Timing Diagram. EFM signal uses the internal Shift Register to input the 14 bits of the EFM demodulation signal (3 Merge Bits removed from the 17-bit EFM demodulation signal) as the EFM demodulator's CDEFM[13:0] signal. The 8 Data bit is converted to 14 channel bit according to the conversion table, and demodulation output EFMD[7:0] is output.
PLCK EFMI(NRZ) NRZI By PLCK NRZ
NRZI Conversion Timing Diagram
129
S5L9250B
DATA SHEET
The NRZI-converted EFM signal uses the internal Shift Register to input the 14 bits of the EFM demodulation signal (3 Merge Bits removed from the 17-bit EFM demodulation signal) as the EFM demodulator's CDEFM[13:0] signal. The 8 Data bit is converted to 14 channel bit according to the conversion table, and demodulation output EFMD[7:0] is output. Frame Sync (24 Channel Bit Length) detection also uses internal Shift Register to prevent the detection of mistaken sync by setting Window sections. It outputs Frame period's WFCK signal, and the EFM Symbol Data period, SYMCK. If the Frame sync and inserted Frame sync coincide when detecting sync signals, the GFS (Good Frame Sync) is output to the Pin. I/O Definition Symbol PLCK EFMI EFMD[7:0] DFRSY CDEFM13:0 Related MICOM Control BIT I/O I I O I/O Channel Bit Clock EFM NRZ INPUT EFM Demodulation output Detected Frame Sync Out of CD DATA 17 bits, 14 bits of CD Data excluding the 3 Merge bits EFM control-related MICOM BIT 33 SYMCLK generated in FRAME SYNC section VCO CLOCK for CLV use, 7.35 kHz "H" when detected Frame Sync and inserted Frame Sync coincide Description comment for one-chip from PLL from PLL to internal SRAM Internal signal Internal signal FROM/TO MICIF
SYMCK
WFCK GFS
O
O O
to CD-DSP to CD-DSP PAD, to CLV Part
Related Register 5Ah(W) Reset value bit 7 0 bit 6
SBFLUSHEN
bit 5 -
bit 4 -
bit3 WSEL1 0
bit 2 WSEL0 0
bit 1 GSEL1 0
bit 0 GSEL0 0
EFMCTRL1 SUBCON
0
5Bh(W) EFMCTRL2 Reset value
bit 7 -
bit 6
CK33MSEL
bit 5 -
bit 4 -
bit3 -
bit 2 WLOCK 0
bit 1 GFSDET 0
bit 0 WNDRST 0
0
130
DATA SHEET
S5L9250B
SPINDLE MOTOR CONTROL Characteristics CD AUDIO/ROM CLV (4X, 8X), CAV(12X, 16X, 24X, 32X, 40X, 48X) Wide PLL compatible MICOM Setting CAV 256-step High Resolution Control Range Selection Mode Frequency, Phase Error Gain setting Mode Output Offset Increase/Decrease feature (compatible with various different motors) Low Power Deceleration Prohibition Mode Rough CAV Mode Emergency Monitor (Detects Reverse Rotation, Speeding) Carries out Digital EQ according to speed Independent Disc Motor Control ; Direct output to Motor Driver using AFC, APC, and Loop Compensator configuration Block Description 1) Characteristics (1) CLV (Constant Linear Velocity) ; Controlled using the Frame Sync separated from Channel Bit Data as the comparative signal. 2 types (CD: 4X / 8X) of different speed modes. (2) CAV (Constant Angular Velocity) ; Controlled using the FG signal as the comparative signal. Selects number of disc rotation by MICOM Data (Rotation / standard Clock Data selection). Number of rotation control range : 245 - 15697 RPM (3) Rough CAV ; When executing track jump in CLV Mode, automatic conversion to CAV Mode is carried out so that MICOM can directly set the number of disc motor revolutions. Lock Down is usually generated during Track Jump, and when controlled to near the number of tracks being jumped, PLL can easily go to Lock without sudden changes in the Data Rate.
131
S5L9250B
DATA SHEET
AFC / APC Gain Selection ; . AFC Auto Gain Down Selection . By OAK DSP Core . 3 STEP PWM Carrier frequency change 4 STEP AFC linear form control range selection 4 STEP AFC Control Dead Zone selection 2 STEP APC Control range selection Forced output Mode: Forced APC output OFF, output Hold 4 STEP Phase Error Sampling frequency selection Phase Offset adjustment Number of MOTOR Poles: 6 Poles (Standard 3 pulse /revolution) 12 Poles (6 pulse /revolution) FG Division Ratio Selection Possible : Division by factors of 1/2/3/6
132
DATA SHEET
S5L9250B
Block Diagram
ROTSEL,ROVS[2:0] DIRROT FG CAVR[9:0] INIT_VAL FCAVCK CAVCK[2:0] CK34 SPD[2:0] DCTL 1/J 1/3.5 PCAVCK MODE FCG[1:0] SELECT
PC_RESET PCOFFS[7:0]
REV/ROV Detect
REVINT,ROVINT
CAV_CNT [10:0] PCAV_CNT [7:0]
TMP_CAV [10:0] TMP_PCAV [7:0]
FNCW[1:0] FPLUS PCR RCAV FAGD ULHD
1/L
FCCK WFREF
AFC_CNT [10:0]
TMP_FCV [10:0]
FCW[1:0] APC_CNT [7:0]
'0' PCG[1:0] TMP_PCV [7:0] MX
D-EQ & Gain Adjustment
1/M PCW[1:0] GFS 1/N
P_WFREF PCCK PCEN
FPCV[7:0] LOCK_CNT [5:0] CLVLOCK STOP,KICK,SMON[1:0] FCG[2:0],PCG[2:0] 2'S COMP. CLVLOCK
WFCK
WFCK2 RIS[1:0] FAL[1:0] PWM_CNT [6:0]
PWMCA[1:0]
1/K
PWM_OUT
SMOFP
PWMCK
PAD
Figure 3. Block Diagram of the Spindle Motor Control Block
133
S5L9250B
DATA SHEET
I/O Definition Symbol CK34 RSTB DIRROT FG WFCK GFS FPLUS FAGD RCAV FCW1 - 0 FNCW1 - 0 SPD2 - 0 DCTL SMON1 - 0 SPOLAR POFFS7 - 0 PWMCA1 - 0 PCEN PCR PCW1 - 0 START BRAKE ROTSEL ROVS2 - 0 RIS1 - 0 FAL1 - 0 CLVLOCK REVINT ROVINT SPINDLE I/O I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O Reset ( Low Active ) Motor Rotate Direction Frequency Generator ( for CAV ) EFM Dem. Frame Sync Good Frame Sync Plus Only Mode Frequency Auto Gain Down Auto Gain Down FC Control Width FC No Control Width Spindle Control Speed Select Motor Control Method Select Motor Control On Motor Control Output Polarity Phase Control Offset PWM Carrier Frequency Select Phase Control Enable Phase Control Range Setting Phase Control Period Motor Kick Motor Brake Disc Rotation Direction Select Overrun Detect Condition Setting CLV Lock Condition CLV Unlock Condition CLV Lock Reverse Rotate Interrupt Overrun Interrupt PWM (Frequency + Phase) Output Description XTAL Clock Input for CD (33.8688 MHz) comment for one-chip EXTERNAL EXTERNAL EXTERNAL(MOTOR) RF EFM DEM. EFM DEM. CTR REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG CTL REG MONITOR MICOM I/F MICOM I/F PAD
134
DATA SHEET
S5L9250B
C1/C2 ERROR CORRECTION Block Description Double correction for C1 & quadruple correction for C2, using an internal 16 K bit SRAM. Block Diagram
Syndrome modified Syndrome ECC Control Euclid Algorithm Syndrome Chien search error correction control bus data bus 16 KSRAM
Detailed Function Description C1 pointer (flag) for prevention of C2 miscorrection, according to the C1 error status (c1flg). C2 pointer (flag) for Interpolation (CD-Audio) or continuous ECC (CD-ROM), according to the C2 error status (c2flg). C2 error corrector executes 3 symbol erasure, 4 symbol erasure or 2 symbol error correction according to the MICOM register (eramod, c2ecc). Monitoring of correction status using the MICOM register (c1ebyte, c1ecode, c2ebyte, c2ecode).
I/O Pins No external pins (PAD) MICOM Registers MICOM write register . eramod, c1flg, c2flg, c2ecc MICOM read register . c1ebyte, c1ecode, c2ebyte, c2ecode
135
S5L9250B
DATA SHEET
MMU (MEMORY MANAGEMENT UNIT) SRAM Resource Since frame sync period is 7.35 kHz (=4.3218 MHz/588 bits) and the amount of ECC data within 1 frame is 32 bytes, the speed in which data is input into the disc is 235.2 k bytes per second. However, of the ECC data, 8 bytes are parity data, which means that the actual amount of audio data input into the disc is 176.4 k bytes. Also, the data output to DAC is 44.1 kHz, stereosignal is output in units of word (=16 bits), and the output data is 176.4 k bytes per second. Therefore, the ratio of the input and output signal matches at 1:1 on average, but the EFM input data may show a slight difference according to the disc revolution, so you must take this difference into consideration when decoding. Usually, the input data is decoded with a jitter margin of 4 frames. Jitter is the change in EFM input due to various reasons such as disc rotation speed. The change in EFM input amount may overwrite the data being executed, so to prevent this, there is a jitter margin of 4 frames. This means that since you need more than 108 frames of data to carry out ECC, the difference between the ECC read point and ECC write point is maintained at within 4 frames so that this area is not damaged through EFM write (refer to the figure below). Frame0 EFM write point 1 2 3 4 ECC (DAC) read point 5 SRAM
Of the resources that access internal memory, there are EFM input and ECC that corrects errors, and the Interpolator that interpolates the error. * EFM Write
Within 1 Frame sync period, 32 bytes out of 588 bits are stored in the internal memory. The remaining data are merge bits, sync patterns, and subcode bytes. * ECC R/W
Address 1) Normal Read Address : Interleaved Data + Parity Data 2) Read/Write Address for Error Data 3) Read/Write Address for C1/C2 data Memory Access Occurrence C1 decoding Data Read C1 Correction Read/Write C1 Flag write : 32 bytes : MAX 2/2 bytes : 1 byte
136
DATA SHEET
S5L9250B
C2 decoding Data Read C1 flag Read C2 correction Read/Write C2 flag Write C1 flag Read * : 28 bytes : 28 bytes : MAX 4/4 bytes : 12 bytes : 24 bytes
Interpolation Read Address - Data + C2PO
To carry out Interpolation, you need 4 bytes of data read and 2 bytes of C2 erasure read per 44.1 kHz. Memory Access Timing Analysis 1x
Number of Data Access EFM ECC Interpolation 32 bytes per 7.35 kHz 137 bytes per 7.35 kHz 6 bytes per 44.1 kHz (36 bytes per 7.35 kHz) 181 bytes per 7.35 kHz Frequency 235.2 kByte/sec 1006.95 kByte/sec 264.6 kByte/sec
Nx
Number of Data Access 32 bytes per 7.35 * N kHz 137 bytes per 7.35 * N kHz 6 bytes per 44.1 * N kHz (36 bytes per 7.35 * N kHz) 1.507 MByte/sec 362 bytes per 7.35 kHz 3.014 MByte/sec Frequency 235.2 * N kByte/sec 1006.95 * N kByte/sec 264.6 * N kByte/sec
Total
Memory Size & Map The reason why Memory size is 16K bits (2048 bytes) is because you need 108 frames of data for error correction. The memory is needed as the error correction decoding buffer, audio out buffer, and EFM write's jitter margin. The memory use of each part is shown in the table below. Content Data ECC Interpolation C1 Erasure C2 Erasure Audio Data C2 Erasure Size 1560 bytes 109 bytes 1 bytes 48 bytes 3 bytes 51 bytes 1670 bytes 1849 bytes Sub-Total Total
EFM Data 128 bytes 128 bytes As shown in the table above, you need a minimum of 1849 bytes, and there is a reserve of 199 bytes (approximately 6 frames) in case of a change in EFM input rate. MICOM sends a speed control command to the spindle servo to carry out the memory overflow/underflow check, in case jitter exceeds the margin of 4 frames. Memory must be used efficiently to carry out decoding within 16 k bits. This is not possible using the address generation method by ALU operation, so you need to store the memory map in ROM for optimization.
137
S5L9250B
DATA SHEET
Address Generation EFM Write Address ECC R/W Address 1) Normal Read Address : Interleaved Data + Parity Date 2) Read/Write Address for Error Data 3) Read/Write Address for C1/C2 data Interpolation Read Address - Data + C2PO
138
DATA SHEET
S5L9250B
Priority Control As we saw above, the blocks that access the memory are EFM, ECC, and the Interpolator. There is a priority between these blocks, and the MMU block allows them memory use according to this priority. First priority is given to the Interpolator since there is no way to restore the music once it stops. The EFM that accepts data from the optical disc has second priority, and the ECC that reads data from the buffer and corrects errors has the lowest priority. Also, for active memory access, the other blocks excepting the ECC cannot demand continuous access to data, and is not able to demand data again within 6 clocks of the movement frequency after receiving data. The flowchart given below shows the priority control.
Priority Control clk itp_req itp_gnt itp_addr efm_req efm_gnt efm_addr ecc_rd_req ecc_wr_req ecc_gnt ecc_addr RAM_Address RAM_DataIn RAM_DataOut
Read Address ITP EFM EFM ITP EFM ECCrd ECCrd Write Address ECCwr ECCwr ECCwr Address Address
Bus Holder
The protocol between the MMU block and each request blocks during read/write are shown in the figure below. Although the number of clocks needed for 1 data access is 3, data access is possible at each clock because of pipeline action.
139
S5L9250B
DATA SHEET
MMU I/F Protocol Read Operation clk rd_req rd_gnt rd_addr Offset_Addr RAM_Addr RAM_DataOut
Address Offset_Add r
Read_Frame_Counter + Offset_Addr
Data_Out
Bus Holder
MMU I/F Protocol Write Operation clk wr_req wr_gnt wr_addr Offset_Addr RAM_Addr RAM_DataIn RAM_DataOut
Address Offset_Add r
Write_Frame_Counter + Offset_Addr
Data_In Data_Out
Bus Holder
* RAM_DataOut is 8 bits.
140
DATA SHEET
S5L9250B
Internal SRAM The I/O and Block Diagram of the SRAM made using the ASIC Design kit is shown below, together with the timing diagram. The SRAM output is valid only for 1 clock period. The output block has a busholder attatched to maintain previous data because of high impedance output.
Internal SRAM Block Pin I/O
DI A OEN WEN CSN CK DOUT
SRAM I/F READ TIMING
minckl minckh
CK CSN WEN OEN A
t as t acc td
a
tws
twh
t ah
DOUT
SRAM I/F WRITE TIMING
CK CSN WEN OEN A
t as tds t dh
DATA X
tws
twh
t ah
DI DOUT
DATA X
tacc
td
a
141
S5L9250B
DATA SHEET
MMU Block I/O
Port clk4M i_rstb i_EfmReq i_EfmAddr i_EccRdReq i_EccWrReq i_EccAddr i_ItpReq i_ItpAddr i_EfmWrData i_EccWrData I_EccCnt i_AcptEccCnt i_RFCntEnb i_WFCntEnb i_JitterCntEnb i_MUTE i_RAMCLR i_KICK_SERVO i_KICKEN i_AUDRSTEN
I/O I I I I I I I I I I I I I I I I I I I I I
To/From CLKGEN CLKGEN EFM EFM ECU ECU ECU ITP ITP EFM ECU ECU ECU CLKGEN CLKGEN CLKGEN MICOM MICOM SERVO MICOM MICOM MMU Reset signal EFM write Request EFM Offset Address ECC Read Request ECC Write Request ECC Offset Address Interpolation Read Request Interpolation Offset Address EFM Write Data ECU Write Data EccCnt latch Enable Signal EccCnt latch Enable Signal
Comment MMU clock (CAV : plck/2, CLV : x'tal/16)
Read Frame Counter Count Enable Signal Write Frame Counter Count Enable Signal Jitter Calculation Enable Signal Audio mute signal ECC SRAM Clear signal Kick, Lens Kick input signal Signal that decides whether to use the Servo's Kick signal when controlling DASP jitter. Signal that decides to use AUDRST input from MICOM after jump in the Audio Buffering Mode as the memory controller's jitter control signal. Signal that selects "H" at the end of a jump from MICOM when executing a jump in Audio Buffering Mode. Signal that decides whether or not to use the PHOLD_EQ signal in the jitter control conditions. PHOLD + Time to PLL LOCK + EHD_DLY[3:0] Signal that decides whether to use the PHOLD_VCO signal in the jitter control conditions PHOLD + VHD_DLY[3:0] Jitter Monitoring Signal ( active High ) EFM Grant Signal ECU Grant Signal
i_AUDST i_MPEQ i_PHOLD_EQ i_MPVCO i_PHOLD_VCO o_Jitter o_EfmGntMask o_EccGntMask
I I I I I O O O
MICOM MICOM CLKGEN MICOM CLKGEN MICOM EFM ECU
142
DATA SHEET
S5L9250B
Port o_ItpGntMask o_EndOfTrx o_RAMCLRReset o_WBC o_RBC o_CSNMask o_RamWENMask o_RamAddrMask o_RamDataInMask
I/O O O O O O O O O O
To/From ITP ECU MICOM PS PS SRAM SRAM SRAM SRAM Interpolation Grant Signal
Comment Indicate signal that is end of tranfer SRAM Clear complete signal Write Frame Counter output signal Read Frame Counter output signal memory CSN signal memory WEN signal memory address write date to memory
143
S5L9250B
DATA SHEET
SUBCODE INTERFACE (INCLUDING SUB-Q) Block Description extracts 'control & display data' that called Subcode from EFM data stream. Subcode Q 98 bits : 2 bits for S0 and S1, 80 data bits, 16 CRC bits Block Diagram
EFM data S0S1 sync
Subcode data register(P - W)
EXCK SBSO SCOR SBQERR SBQINT MICOM interface
subQ
CRC Check
subQ register
SBQDAT
Figure 4. Subcode Handling Block Diagram Detailed Function Description The 8-bit subcodes P - W can be read from SBSO by inputting EXCK. subQ 80 bits and CRC check output can be read from MICOM register.
S0,S1[2]
CONTROL[4]
ADR[4] 80-bit
DATA-Q[72]
CRC[16]
S0,S1[2]
96-bit 98-bit
Figure 5. SUB-Q Channel Format
144
DATA SHEET
S5L9250B
I/O Pin Symbol SCAND SCOR SBCD[7:0] WFCK EXCK SBSO WFCKO SCORO SBQERR SBQDAT[7:0] SBQINT I/O I I I I I O O O O O O Description Subcode Sync (S0 x S1) Subcode Sync (S0+S1) EFM decoded Subcode Data Write Frame Sync Subcode Data Readout Clock Subcode P to W serial output Delayed WFCK(Write Frame Clock) when either S0 or S1 is detected, SCORO is high CRC check output MICOM read data bus for subQ (10 Byte) subcode sync interrupt comment for one-chip from EFM from EFM from EFM from EFM from external PAD to external PAD to external PAD to external PAD to MICOM UCOMIF
MICOM Register MICOM write register . SBQIEN : subcode sync interrupt request enable Micom read register . SUBINT : subcode sync interrupt . SBQD[79:0] : SBQ data register Address 73h(r) 74h(r) 75h(r) 76h(r) 77h(r) 78h(r) 79h(r) 7Ah(r) 7Bh(r) 7Ch(r) bit 7 CTL3 TNO7 INDEX7 MIN7 SEC7 FRM7 ZERO AMIN7 ASEC7 AFRM7 bit 6 CTL2 TNO6 INDEX6 MIN6 SEC6 FRM6 ZERO AMIN6 ASEC6 AFRM6 bit 5 CTL1 TNO5 INDEX5 MIN5 SEC5 FRM5 ZERO AMIN5 ASEC5 AFRM5 bit 4 CTL0 TNO4 INDEX4 MIN4 SEC4 FRM4 ZERO AMIN4 ASEC4 AFRM4 bit3 ADR3 TNO3 INDEX3 MIN3 SEC3 FRM3 ZERO AMIN3 ASEC3 AFRM3 bit 2 ADR2 TNO2 INDEX2 MIN2 SEC2 FRM2 ZERO AMIN2 ASEC2 AFRM2 bit 1 ADR1 TNO1 INDEX1 MIN1 SEC1 FRM1 ZERO AMIN1 ASEC1 AFRM1 bit 0 ADR0 TNO0 INDEX0 MIN0 SEC0 FRM0 ZERO AMIN0 ASEC0 AFRM0
145
S5L9250B
DATA SHEET
SUBCODE Output I/F (for CD-G)
WFCKO
SCORO
S0
S1
EXCK
SBSO
P Q R S T UVW
MICOM Register MICOM write register . SBQIEN : subcode sync interrupt request enable Micom read register . SUBINT : subcode sync interrupt . SBQD[79:0] : SBQ data register
S0S1 WFSY 1 SQCK 1 2 3 4 5 6 7 8
SQDT
2
Q
R
S
T
U
V
W
3
c : After WFSY becomes falling edge, SQCK becomes 'L' for about 10sec. e : Subcode P is output if S0S1 is 'L', and subcode sync S0 and S1 are output if 'H'. e : If pulses are input into the SQCK terminal over seven, subcode data (P,Q,R,S,T,U,V, W) are repeated.
146
DATA SHEET
S5L9250B
S0S1 0 WFSY 1 2 3 4 5 6 ...... 95 96 96
SQCK SQDT P Q R S T U V W
* * *
1 SUBCODE SYNC = 98 EFM FRAMEs (1 EFM FRAME = 7.35 kHz, 1 SUBCODE SYNC = 75 Hz) 98 EFM FRAMEs = 2 Bytes for SUBCODE SYNC(S0, S1) + 96 Bytes for SUBCODE DATA 96 Bytes SUBCODE DATA = 1(P) Bit x 96 + 1(Q) Bit x 80 + 16 Bits(CRC for EDC) for CDP + 6 (R - W) Bits x 96 for CDG
147
S5L9250B
DATA SHEET
CD AUDIO PROCESSOR (INTERPOLATION + 1-BIT DAC) Block Description Interpolation : previous data hold + average Digital attenuation De-emphasis 4Fs over sampling digital filter 16-bit digital-to-analog converter Analog post filter Block Diagram
16K SRAM
corrected data Interpolation C2PO
selector Digital Attenuation
for nx-to-1x audio playback De-Emphasis Digital Filter DAC
analog post-filter
L-ch R-ch
Detailed Function Description Double speed operation of internal DAC output Digital attenuation is a volume control of 64 levels with mute. Digital filter performs 4X interpolation. Its output data rate is 4Fs for normal speed mode and 8Fs for double speed operation. Digital sigma-delta modulator of bit-stream type has the MF (Multiple Feedback) topology, and it performs a noise-shaping function. The modulator shapes the quantization noise by suppressing its in-band component and pushes the noise energy outside of the band-of-interest without deteriorating the audio input signal. The analog postfilter is comprised of the SC-postfilter and anti-imaging filter. The SC-postfilter removes the quantization noise shaped to out-of-band by the digital modulator. This Analog filter has good clock jitter characteristics and a very linear characteristic.
148
DATA SHEET
S5L9250B
I/O pins 1-bit DAC block (from digital attenuator - analog audio) Symbol MSCK MCK MDATA MLD DN DEEM LRCK I/O I I I I I I I Description Master Clock Input (384Fs for 1X/2X playback) MICOM Command Clock Input MICOM Command Data Input MICOM Command Load Input (When Low, load) High is Double (2Fs) Mode, Low is Normal(1Fs) Mode. De-Emphasis On/Off. "H" is enabled. "L" is disabled. Sample Rate Clock Input from MICOM reg. from subcode or MICOM reg. (or external input PAD) from interpolation or ATAPI controller (or external input PAD) comment for one-chip from clock generation MICOM interface for digital attenuation
BCK SDATA BIST_MODE Tsel 1bitIOL 1bitIOR FS64 Vref Iref AoutR AoutL ERROR DONE VBB VSSA VDDA
I I I I I/O I/O I/O I/O I/O O O O O G G P
Bit Clock Input Serial Digital Input Data Bist On/Off Select. "H" is Bist On, "L" is DF Test On I/O direct selection for Test Pins (1bitIOL, 1bitIOR) "H" is Input, "L" is Output 1-bit Input for Analog Postfilter of L-CH (Tsel = H) 1-bit Output for Digital Sigma-Delta Modulator (Tsel = L) 1-bit Input for Analog Postfilter of R-CH (Tsel = H) 1-bit Output for Digital sigma-delta Modulator (Tsel = L) 64xSampling Clock Input for test, Enabled if Tsel = H. 64Fs Clock Output if Tsel=L Reference Voltage Output for Bypass Test Pin for Analog Supply Current Analog Output for R-CH Analog Output for L-CH Test Pin for Embeded memory BIST(BIST_MODE="H") or DF test(BIST_MODE="L") Ouput pin Test pin for embeded memory BIST(BIST_MODE="H") or DF test(BIST_MODE="L") output pin Analog Ground Analog Ground Analog Power Supply required PAD PAD for test required PAD required PAD PAD for test PAD for test Analog Power PAD for post analog-filter test mode selection test mode selection PAD for test PAD for test PAD for test
149
S5L9250B
DATA SHEET
Audio Interface Symbol C2PO LRCKO I/O O O C2 error pointer Sample Rate Clock Input Description comment for one-chip for externel interface output PAD from interpolation or ATAPI controller (or external PAD)
BCKO SDATAO
O O
Bit Clock Input Serial Digital Input Data
MICOM Register
MICOM Write Register . DN : normal/double speed mode for 1-bit DAC . DEEM : De-Emphasis enable . Digital attenuation level : specific MICOM interface timing format Timing Chart Audio data input . for normal speed : MSCK = 384Fs, BCK = 32Fs, LRCK = 1Fs . for double speed : MSCK = 384Fs, BCK = 64Fs, LRCK = 2Fs
MSCK BCK LRCK SDATA
MSB 14
R-CH DATA
13 2 1 LSB MSB 14
L-CH DATA
13 2 1 LSB
MICOM Interface
MCLK
LSB
MSB M1 M2 M3 M4 M5 D(Hex) 5(Hex) Over 350ns needed
Don't Care
MDATA
Don't Care
M
MLD
The Interface shown above is that of the DAC core. Design configuration outside the DAC core must take this format into consideration.
150
DATA SHEET
S5L9250B
Out of the interface formats shown below, the CD-DSP output timing supports the "Toshiba DSP Interface format" and"Sony-24-Clock DSP interface format-1" , andthe S5L9250B's built-in DAC input timing for nx-to-1x supports the"EIAJ (16-bit) Audio Data Interface format"and "Philips 12S (16-bit) audio data interface format" .
CD-ROM, V-CD OUTPUT INTERFACE FORMAT (TO CD-ROM DECODER)
Toshiba 16-Clock DSP Interface Format
1) CD-ROM, V-CD OUTPUT Interface Format (to CD-ROM DECODER)
- Toshiba 16-Clock DSP Interface Format
BCKO LRCKO SDATAO C2PO MSB 15 14 13 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
H - Left Channel , L - Right Channel 11 10 9 8 7 6 5 4 3 2 1 LSB 0
Upper Byte Flag(H=Error)
Lower Byte Flag(H=Error)
- Sony 24-Clock DSP Interface Format-1
BCKO LRCKO SDATAO C2PO MSB 15 Upper Byte Flag (H=Error) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0
H - Left Channel , L - Right Channel 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0
Lower Byte Flag(H=Error)
151
S5L9250B
DATA SHEET
2) CD-AUDIO OUTPUT Interface Format (to CD-ROM DECODER)
- Toshiba 16-Clock DSP Interface Format
BCKO LRCKO SDATAO C2PO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
H - Left Channel , L - Right Channel MSB 15 14 13 12 11 10 9 8 7 6543 Channel Error Flag (H=Error)
2
1
LSB 0
- Sony 24-Clock DSP Interface Format-1
BCKO LRCKO SDATAO C2PO MSB 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0
H - Left Channel , L - Right Channel 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0
Channel Error Flag (H=Error)
152
DATA SHEET
S5L9250B
3) CD Audio Interface Format for 1-bit DAC (from CD-ROM DECODER)
- EIAJ (16-bit) Audio Data Interface Format
ABCK ADAT AWCK 22 23 0 1 2 3 4 5 6 7 8 9 10 1112 13 1415 1617 1819 2021 22 23 0 1 2
10
15
1413 12 1110 9 8 7 6 Left Channel Data
54 3 2 1 0
15
- Philips I2S (16-bit) Audio Data Interface Format
ABCK ADAT AWCK 10 212223 0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223 0 1 2
15 14 121110 9 8 7 6 5 4 3 2 1 0 13 Left Channel Data
1514
153
S5L9250B
DATA SHEET
Block Description The goal of the Digital audio interface block is to transmit the data in the CD disc serially into the surrounding systems. This interface method has the advantage of needing only one pin for transmission. In other words, there are no additional pins needed such as separate clocks. Because of this advantage, it is utilized not only in audio systems for home use, but also for professional use.
X
Channel 1
Y
Channel 1
Z
Channel 1 SubFrame 1
Y
Channel 1 SubFrame 2
X
Channel 1
Y
Channel 1
Frame 191
Frame 0 Start of block
Frame 1
SPDIF (Sony-Philiiips Digital audio Interface) This interface is called SPDIF because Sony and Philips came up with the Digital audio interface method for CDs, and its regulations are registered in the AES (Audio Engineering Society). SPDIF serially transmits data and is sensitive to background noise. To overcome this disadvantage, the digital out data is transmitted after being demodulated into biphase form. Phase0 is given a different value from the previous data's phase1 value. If the source data is '0', phase1 is given the same value as phase0, and if it is '1', phase1 is given a different value from phase0.
0 3 4 AUX 78
LSB
27 Audio Data
MSB
28 V
29 U
30 C
31 P
Preamble Preamble AUX Data Audio Data Valid Data User Data Channel Status Parity Data
Structure of Format Each subframe is configured of 32 time slots, and a subframe includes audio data. 2 subframes make 1 frame, which as Left, Right stereo signal components. 192 frames make 1 block, which is the control bit information unit.
fs = 44.1 kHz
128 fs bit0 Digital Audio Out bit1 bit2 bit3 bit4 bit5 bit6 bit7
....
bit n bit24 bit25 bit26 bit27 bit28 bit29 bit30 bit31
Source Coding
Channel Coding (Biphase Mark) Preamble Z
154
DATA SHEET
S5L9250B
Subframe Format Preamble (4 bit) : The Preamble has the sync data of each subframe and block, and preamble data is not converted into biphase signal to maintain the sync data's uniqueness. However, it starts with the opposite value of the previous symbol's phase1 value. The Preamble needs three patterns to tell apart left, right, and the beginning of a block, which are shown below. Preceding state "X" "Y" "Z" 0 Channel Coding 11100010 11100100 11101000 1 00011101 00011011 00010111 Subframe 1 Subframe 2 Subframe 1 and block start
Preamble 'X' is channel 1's sync., and preamble 'Y' is channel 2's sync. Preamble 'Z' is used to show the block's start sync. The reason why there are two sync patterns for each preamble is because the value is reversed according to the phase of the previous data. 2) AUX (4 bits) : auxiliary data area. 3) Audio Data (20 bits) : Although the resolution of the audio data transmitted to Digital out for CDs is 16 bits, it can be 20 or 24 bits by augmenting the audio data area to the AUX area. This are is LSB first. 4) Validity Bit (1 bit) : If Studio sample word can be converted into analog audio signal, validity bit is set to '1'. If not, it is set to'0'. In the case of CDs, it is set to'0'. 5) User data (1 bit) : CDs use this area to transmit subcode data. 6) Control Status Data (1 bit) : Data is input by each subframe, and 192 subframes make one Control status data. There are the consumer mode and professional mode in this area, and the 4th generation CDP supports consumer mode. For CDs, control status data has the following meaning. Bit 0 1 2 3 4 5 6-7 8 - 15 16 - 19 20 - 23 24 - 27 28 - 29 30 - 191 0 : Consumer use, 1 : Professional use 0 : Normal Audio, 1 : Nonaudio Mode 0 : Copy Prohibit, 1 : Copy Permit 0 : No Preemphasis, 1 : Preemphasis Reserved (= 0) 0 : 2 channel, 1 : 4 channel 00 : mode 0, reserved 10000000 : 2 channel CD player User bit channel = CD Subcode bit optional Source number ( = 0000) Channel number ( = 0000) Sampling frequency : 44.1kHz = 0000 Clock accuracy 00 : Normal accuracy, 10 : High accuracy, 01 : Variable speed Don't care ( all zero ) Description
155
S5L9250B
DATA SHEET
BLOCK I/O Name i_rstb i_LRClk clk128fs i_DIGOUTEN i_EMPH i_CpyRgt i_AudData i_SubData I/O I I I I I I I I To/From CLKGEN CLKGEN CLKGEN MICOM SUBCODE SUBCODE ITP SUBCODE LR Channel Clock = fs Data Transfer Clock = 128 fs Digital audio out block enable signal emphasis on/off 1 : Copy Permit, 0 : Copy Protect 16 bits Audio Data 8 bits Subcode Data Contents SPDIF Block Reset Signal
o_DigAudOut O PAD Digital Audio serial output This block can be used in both Nx Audio Buffering Mode (CAV Mode) and KS9245's AUDIO Bypass Mode. : However, in KS9245's AUDIO Bypass Mode, D/Audio Out signal must be input from outside the CD-ROM Decoder. (So if you don't use Audio Buffering Mode, you must use the D/audio Out Block of the CD-DSP. In that case, features such as stereo, mono, and swap provided by the D/AUD block are not provided, and is output in stereo only mode.) :CAV Mode.
MICOM I/F
CHARACTERISTICS
* MICOM I/F Mode 1) Intel Mode (8051) : Direct Access Register Mode support. 2) Motorola Mode (68HC11) : Direct Access Register Mode support. Address is latched at ALE's falling edge. Apart from the basic MICOM I/F signal, you can set the Intel, Motorola, and indirect Mode by setting TEST1, TEST2, TEST3 and TEST4 PIN : Please refer to P163. 3) Indirect Access Register Mode support.
156
DATA SHEET
S5L9250B
MICROPROCESSOR INTERFACE
Multiplexed Intel Mode Register Read/Write Timing Microcontroller Read Cycle
tAS tRD
tALE
tRDLY
tRC
tAH
ALE tRDH tCS RDB AD[7:0] CSB
address data in address data in
tRP tRDS tCH
tDAR
Microcontroller Write Cycle
tAH
tALE ALE tCS
tRDLY
tDLY
tWDS WRB AD[7:0] CSB
address data out
tWP tWDH tCH
address
data out
Parameter ALE Pulse Width Address Setup Time Address Hold Time Chip Select Setup for Read/Write Command Chip Select Hold for Read/Write Command ALE Active from Read/Write Rising Edge Delay Write Pulse Width Read Pulse Width Data Pulse to next Address Valid Data setup Time for Write Data Hold Time for Write ALE Falling to RDB/WRB Falling Read Data Setup Time Read Data Hold Time
Symbol tALE tAS tAH tCS tCH tDLY tWP tRP tDAR tWDS tWDH tRDLY tRDS tRDH
Min. 1 Sysclk 10 5 10 0 0 2 Sysclk 3 Sysclk 10 10 10 15 1 Sysclk 0
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
157
S5L9250B
DATA SHEET
Multiplexed Motorola Mode Register Read/Write Timing
tAH AD(7:0) - in Add tAS tALE In
tDH
tDELY
ALE tCSH CS tCS tARW tRWS DSB tDS R/WB (Write) tDA AD(7:0) - out R/WB (Read) Out tRDH tDSP tDSL
tHRW
Parameter ALE Pulse Width Address Setup Time Address Hold Time Address Valid Before Read/Write Command Chip Select setup for Read/Write Chip Select Hold for Read/Write R/WB Setup Width DS R/WB Hold Width DS DSB Pulse Width DSB Recover Time Data Setup Time for Write Data Hold Time for Write Read Access Time DSB to ALE Falling Edge Delay Read Data Hold Time
Symbol tALE tAS tAH tARW tCS tCH tRWS tHRW tDSP tDSL tDS tDH tDA tDELY tRDH
Min. 1 Sysclk 10 10 15 10 0 5 5 3 Sysclk 1 Sysclk 10 10 1 Sysclk 1.5 Sysclk 0
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2 Sysclk
ns ns
158
DATA SHEET
S5L9250B
Indirect Access Register Mode Read/Write Timing
tDA AD(7:0) - in tRWB tAS RDB tDH AD(7:0) - out tRWB tAS WRB RSB CS L : Address Port , H : Data Port tWP Valid Data tDS Valid Data tRP
tHZ
tRWH
Parameter WRB Recover Time to next RDB or WRB CS or RSB Setup for Read/Write WRB Pulse Width RDB Pulse Width CS or RSB Hold Time Data Setup Time for Write Data Hold Time for Write Read Access Time Read Data Hold Time
Symbol tRWB tAS tWP tRP tRWH tDS tDH tDA tHZ
Min. 2 Sysclk 10 40 40 6 10 10 10 0
Max.
Unit ns ns ns ns ns ns ns
20
ns ns
159
S5L9250B
DATA SHEET
APPLICATION CIRCUIT (1)
S5L9250B Application Circuit for Servo Block
51 SENSE
2 VREFI 4 RFRP 5 RFCT 6 SBAD 7 CEI 32 RFEN 33 RFDATA 34 RFCLK 8 TZCA 9 TE 10 TELPF 104 22k 104 VREF From RF 11 FE
SERVO BLOCK
50 GPIO8/FOKB
MICOM
17 TRD 18 FOD 12 FELPF 104 15 PPUMP 19 SLED0 20 SLED1
27 GPIO1/PS1 28 GPIO2/SSTOP
900p
15k Vref
RFAMP
DRIVER & Pickup
160
DATA SHEET
S5L9250B
APPLICATION CIRCUIT (2)
CD-ROM DECODER
Pins 104, 105, 107, and 108 must each add application circuits on the exterior. 0.1 uF 10 uF 107 Vref 108 VHALF 104 AoutL 105 AoutR 100 K 1 uF 104 112 VBG 681 5K 110 PWMO 300 104 Control signal from MICOM 5K 12 K 22 K 470 821 117 RVCO 116 RDAC 104 103
** P120's ANALOG SW is used, fixed to 5K until 52X, and needs Switching if used up to 60X.
MICOM
CD-DA I/F 33.8688
54 53
SUBCODE I/F 90 EXCK 92 SBSO 93 WFCKO 97 SCORO
MHz
101 SDATAI 99 BCKI 102 LRCKI 97 CK50M
83 SDATA0 87 BCKO 84 LRCKO 86 C2PO 89 DA OUT
56 SINTB 60 RDB 63 CSB 65 ~ 73
58 WRB 61 ALE 57 ZRST AD[7:0]
CLK GEN
111 PWMI 114 VCTRL
120 RISS 119 VALGC 122 EFMCOMP
1K 681 1K 681 103 10K 681 10K 333
S5L9250B Application Circuit for DATA RECOVERY & PROCESSOR
37 TEST1 41 TEST2 42 TEST3 44 TEST4 PULL-DOWN or PULL-UP
125 LPF0 124 LPF1 TO RF 152 126 RFI 128 EQ_CTL 21 SMOFP To spindle 27 SMON To spindle 29 FG FG From RF
161
S5L9250B
DATA SHEET
. MONITER MODE
S5L9250B Monitor Mode Setting Conditions (Normal Operation) * Mmode : Monitor Mode Selection Register Address 4Eh bit 7 MDSP3 bit 6 MDSP2 bit 5 bit 4 bit3 MSERVO3 bit 2 bit 1 bit 0 -
Reset value 0 0 0 * Please refer to . TEST MODE for normal operation conditions. (Normal Operation Conditions) & (4Eh MICOM Data Setting Value) PAD NAME TZCO MIRR PHOLD COUT LOCK GFS C2PO PLCK MDSP[3:0 ]= "1000" EccGnt EfmGnt EccWrReq ItpGnt EccRdReq EfmReq EndOfTrx ItpReq MDSP[3:0]= "0100" frsy p_wfref p_xfref Jitter WfCntEnb RfCntEnb dfrsy JitterCntEnb KICK DFCTO MDSP1 ="0010" MDSP0 ="0001"
MSERVO3 MSERVO2 MSERVO1 MSERVO0 = "1000" ="0100" = "0010" = "0001"
-
-
-
162
DATA SHEET
S5L9250B
. TEST MODE
1.1 BI9250X Test Mode Setting Conditions : Scan Enable Signal(PAD75)
Pin No. Pin Name Normal Normal Normal Intel Motorol a P37 P41 P42 P44 TEST1 TEST2 TEST3 TEST4 L L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H H L L L H L L H H L H L H L H H H H L L H H L H H H H L Indir Nand soak_te _Tree st glue glue_ glue_ind BIST SCAN_ block_in block_m block_in srom_te sdac_te ir MODE MODE tel otorola dir st st _intel motorola
1.2 S5L9250B Block Test Mode Setting Characteristics BI9250X can be operated in various modes b adjusting the values of P37, P41, P42, P44, theTEST1, TEST2, TEST3, TEST4. NORMAL INTEL, NORMAL MOTOROLA, and NORMAL INDIRECT MODE are modes used in normal operation, which makes the MICOM I/F operate in INTEL MODE, MOTOROLA MODE, or INDIRECT MODE. The remaining 6 modes are TEST modes, including NAND TREE TEST, OAK CORE TEST, SERVO ROM TEST, ECC SRAM TEST (BIST), SCAN TEST MODE, BLOCK TEST MODE. You need to set the 4 test pins according to the mode you want. Of the test modes above, Glue Test and block_test adjust TEST1, 2, 3, and 4 for respective use as Intel, Motorola, and Indirect mode.
163

▲Up To Search▲

Price & Availability of S5L9250B01-Q0R0

	To Download S5L9250B01-Q0R0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .